IP Library › Assignment 041870/0455
Patent Assignment
Reel/Frame 041870/0455

Merger

Recorded: 2017-02-16 Pages: 7
Assignor
EZCHIP SEMICONDUCTOR LTD.
Executed: 2017-01-30
Assignee
MELLANOX TECHNOLOGIES, LTD.
26 HAKIDMA STREET, MELLANOX BUILDING, YOKNEAM 2069200, ISRAEL
Covered Properties (84)
Flow Control in a Parallel Processing Environment
Patent: 8,018,849 →
Application: 11/313,895 →
Buffering Data in a Parallel Processing Environment
Patent: 7,668,979 →
Application: 11/313,900 →
Managing Data Flows in a Parallel Processing Environment
Patent: 7,814,242 →
Application: 11/314,254 →
Managing Buffer Storage in a Parallel Processing Environment
Patent: 7,853,774 →
Application: 11/314,270 →
Transferring Data in a Parallel Processing Environment
Patent: 7,461,236 →
Application: 11/314,861 →
Managing Memory in a Parallel Processing Environment
Patent: 7,624,248 →
Application: 11/404,187 →
Mapping Memory in a Parallel Processing Environment
Patent: 7,620,791 →
Application: 11/404,207 →
Directing Data in a Parallel Processing Environment
Patent: 7,793,074 →
Application: 11/404,281 →
Coupling Integrated Circuits in a Parallel Processing Environment
Patent: 7,539,845 →
Application: 11/404,409 →
Protection in a Parallel Processing Environment Using Access Information Associated with Each Switch to Prevent Data from Being Forwarded Outside a Plurality of Tiles
Patent: 7,774,579 →
Application: 11/404,461 →
Managing Cache Memory in a Parallel Processing Environment
Patent: 7,882,307 →
Application: 11/404,641 →
Managing Set Associative Cache Memory According to Entry Type
Patent: 7,461,210 →
Application: 11/404,654 →
Managing Memory Access in a Parallel Processing Environment
Patent: 7,805,577 →
Application: 11/404,655 →
Coupling Data in a Parallel Processing Environment
Patent: 7,636,835 →
Application: 11/404,658 →
Managing Data in a Parallel Processing Environment
Patent: 7,577,820 →
Application: 11/404,958 →
Pattern Matching in a Multiprocessor Environment with Finite State Automaton Transitions Based on an Order of Vectors in a State Transition Table
Patent: 7,805,392 →
Application: 11/564,694 →
Programming in a Multiprocessor Environment
Patent: 9,009,660 →
Application: 11/564,723 →
Pattern Matching
Patent: 7,877,401 →
Application: 11/753,315 →
Packet Processing in a Parallel Processing Environment
Patent: 8,194,690 →
Application: 11/753,325 →
Caching in Multicore and Multiprocessor Architectures
Patent: 7,853,752 →
Application: 11/754,016 →
Caching in Multicore and Multiprocessor Architectures
Patent: 7,853,754 →
Application: 11/754,062 →
Caching in Multicore and Multiprocessor Architectures
Patent: 7,805,575 →
Application: 11/754,118 →
Caching in Multicore and Multiprocessor Architectures
Patent: 7,853,755 →
Application: 11/754,162 →
Compiling Code for Parallel Processing Architectures Based on Control Flow
Patent: 8,250,555 →
Application: 12/028,002 →
Distributing Parallelism for Parallel Processing Architectures
Patent: 8,250,556 →
Application: 12/028,003 →
Communication Scheduling for Parallel Processing Architectures
Patent: 8,291,400 →
Application: 12/028,005 →
Memory Access Assignment for Parallel Processing Architectures
Patent: 8,181,168 →
Application: 12/028,007 →
Coupling Data for Interrupt Processing in a Parallel Processing Environment
Patent: 8,190,855 →
Application: 12/036,918 →
Managing Data Forwarded Between Processors in a Parallel Processing Environment Based on Operations Associated with Instructions Issued by the Processors
Patent: 7,734,894 →
Application: 12/110,871 →
Managing Data Provided to Switches in a Parallel Processing Environment
Patent: 8,127,111 →
Application: 12/110,956 →
Configuring Routing in Mesh Networks
Patent: 8,050,256 →
Application: 12/169,436 →
Configuring Routing in Mesh Networks
Patent: 8,045,546 →
Application: 12/169,442 →
Configuring Routing in Mesh Networks
Patent: 8,151,088 →
Application: 12/169,456 →
Managing Shared Resource in an Operating System by Distributing Reference to Object and Setting Protection Levels
Patent: 8,799,914 →
Application: 12/885,957 →
Low-Overhead Operating Systems
Patent: 8,327,187 →
Application: 12/885,978 →
Managing Cache Coherence
Patent: 8,392,661 →
Application: 12/885,994 →
Supporting Secondary Atomic Operations Using Primary Atomic Operations
Patent: 8,549,249 →
Application: 12/886,013 →
Managing Memory Requests Based on Priority
Patent: 8,886,899 →
Application: 12/886,050 →
Memory Controller Load Balancing with Configurable Striping Domains
Patent: 9,063,825 →
Application: 12/886,136 →
Route Prediction in Packet Switched Networks
Patent: 9,135,215 →
Application: 12/886,163 →
Low Latency Dynamic Route Selection
Patent: 8,934,347 →
Application: 12/886,346 →
Managing Cache Access and Streaming Data
Patent: 9,213,652 →
Application: 12/886,365 →
Condensed Router Headers with Low Latency Output Port Calculation
Patent: 8,572,353 →
Application: 12/886,366 →
Managing Home Cache Assignment
Patent: 8,539,155 →
Application: 12/886,372 →
Managing Cache Coherence
Patent: 8,521,963 →
Application: 12/886,376 →
Configurable Device Interfaces
Patent: 8,799,624 →
Application: 12/886,382 →
Memory-Mapped Data Transfers
Patent: 8,612,711 →
Application: 12/886,386 →
Pattern Matching in a Multiprocessor Environment
Patent: 8,065,259 →
Application: 12/890,996 →
Caching in Multicore and Multiprocessor Architectures
Patent: 8,112,581 →
Application: 12/958,920 →
Caching in Multicore and Multiprocessor Architectures
Patent: 7,987,321 →
Application: 12/966,686 →
Pattern Matching
Patent: 8,620,940 →
Application: 12/977,565 →
Managing Cache Memory in a Parallel Processing Environment
Patent: 8,200,901 →
Application: 12/983,368 →
Pattern Matching in a Multiprocessor Environment
Patent: 8,086,554 →
Application: 13/188,580 →
Caching in Multicore and Multiprocessor Architectures
Patent: 8,234,451 →
Application: 13/190,035 →
Transferring and Storing Data in Multicore and Multiprocessor Architectures
Patent: 8,677,081 →
Application: 13/211,065 →
Flow Control in a Parallel Processing Environment
Patent: 8,635,378 →
Application: 13/229,294 →
Configuring Routing in Mesh Networks
Patent: 8,737,392 →
Application: 13/278,663 →
Configuring Routing in Mesh Networks
Patent: 9,384,165 →
Application: 13/278,676 →
Computing in Parallel Processing Environments
Patent: 8,738,860 →
Application: 13/280,927 →
Packet Processing in a Parallel Processing Environment
Patent: 9,787,612 →
Application: 13/487,361 →
Publication: US 2013/0070588
Managing Cache Memory in a Parallel Processing Environment
Patent: 8,631,205 →
Application: 13/491,413 →
Caching in Multicore and Multiprocessor Architectures
Patent: 8,560,780 →
Application: 13/553,884 →
Compiling Code for Parallel Processing Architectures Based on Control Flow
Patent: 8,949,806 →
Application: 13/588,141 →
High Performance, Scalable Multi Chip Interconnect
Patent: 9,424,228 →
Application: 13/789,801 →
Publication: US 2014/0122560
Caching in Multicore and Multiprocessor Architectures
Patent: 9,514,050 →
Application: 14/047,128 →
Managing Cache Memory in a Parallel Processing Environment
Patent: 9,298,618 →
Application: 14/154,277 →
Flow Control In A Parallel Processing Environment
Patent: 9,329,798 →
Application: 14/159,608 →
Cache Coherency in Multiprocessor System
Application: 14/208,405 →
Global Socket to Socket Cache Coherence Architecture
Application: 14/246,213 →
Computing in Parallel Processing Environments
Application: 14/286,000 →
Managing Shared Resources In An Operating System
Application: 14/450,476 →
Configurable Device Interfaces
Patent: 9,858,200 →
Application: 14/450,527 →
Multi-Core Processor Using Three Dimensional Integration
Patent: 9,886,275 →
Application: 14/508,027 →
Low Latency Dynamic Route Selection
Patent: 9,507,745 →
Application: 14/594,299 →
Computing In Parallel Processing Environments
Application: 14/636,296 →
Programming In A Multiprocessor Environment
Patent: 9,934,010 →
Application: 14/675,935 →
Memory Controller Load Balancing With Configurable Striping Domains
Patent: 9,753,854 →
Application: 14/747,044 →
Route Prediction In Packet Switched Networks
Patent: 9,479,431 →
Application: 14/854,286 →
Managing Cache Access and Streaming Data
Application: 14/967,665 →
Managing Cache Memory In A Parallel Processing Environment
Patent: 9,639,487 →
Application: 15/083,408 →
Flow Control In A Parallel Processing Environment
Application: 15/143,754 →
Configuring Routing in Mesh Networks
Application: 15/201,754 →
High Performance, Scalable Multi Chip Interconnect
Application: 15/244,171 →
Caching in Multicore and Multiprocessor Architectures
Application: 15/368,947 →
Related Assignments (8)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Feb 16, 2017
From: EZCHIP SEMICONDUCTOR LTD.
To: EZCHIP TECHNOLOGIES, LTD.
Reel/Frame 041736/0253 →
Merger Feb 16, 2017
From: EZCHIP TECHNOLOGIES LTD.
To: EZCHIP SEMICONDUCTOR LTD.
Reel/Frame 041736/0321 →
Merger Feb 16, 2017
From: TILERA CORPORATION
To: EZCHIP SEMICONDUCTOR INC.
Reel/Frame 041735/0792 →
Dividend Declaration from Ezchip Semiconductor Inc. to the Stockholder of Record on 6/2/2015 (Ezchip Inc., a Delaware Corporation) Feb 16, 2017
From: EZCHIP SEMICONDUCTOR INC.
To: EZCHIP, INC.
Reel/Frame 041736/0013 →
Purchase Agreement Feb 16, 2017
From: EZCHIP, INC.
To: EZCHIP SEMICONDUCTOR LTD.
Reel/Frame 041736/0151 →
Security Interest Jun 23, 2017
From: MELLANOX TECHNOLOGIES, LTD.; MELLANOX TECHNOLOGIES TLV LTD.; MELLANOX TECHNOLOGIES SILICON PHOTONICS INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 042962/0859 →
Release of Security Interest in Patent Collateral at Reel/Frame No. 42962/0859 Jul 13, 2018
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MELLANOX TECHNOLOGIES, LTD.; MELLANOX TECHNOLOGIES TLV LTD.; MELLANOX TECHNOLOGIES SILICON PHOTONICS INC.
Reel/Frame 046551/0459 →
Assignment of Assignor's Interest May 3, 2019
From: TANDENT VISION SCIENCE, INC.
To: TANDENT COMPUTER VISION LLC
Reel/Frame 049080/0636 →