Managing buffer storage in a parallel processing environment
View Patent ↗An integrated circuit including a plurality of tiles. Each tile comprises a processor; a switch including switching circuitry to forward data words over data paths from other tiles to the processor and to switches of other tiles; and memory coupled to the switch to buffer data transmitted among the tiles. The switches form a plurality of networks among the tiles. At least one of the networks is configured to transmit data among the tiles using an approach that reserves sufficient buffer space in the memories coupled to the switches to avoid deadlock conditions, and at least one of the networks is configured to transmit data among the tiles using an approach to detect and recover from deadlock conditions.
1. An integrated circuit comprising:
a plurality of tiles, each tile comprising
a processor;
a switch including switching circuitry to forward data words over data paths from other tiles to the processor and to switches of other tiles; and
memory coupled to the switch to buffer data transmitted among the tiles;
a plurality of networks among the tiles with each network comprising switches of the tiles and dedicated data paths directly connecting switches of neighboring tiles, with data paths between neighboring tiles including different respective sets of said data paths dedicated to different networks to enable different networks to transfer data over the respective sets of data paths without sharing the same data paths between neighboring tiles, and
at least a first one of the networks configured to transmit data among the tiles reserving sufficient buffer space in the memories coupled to the switches to prevent limited-buffer deadlock conditions from occurring, and at least a second one of the networks configured to transmit data among the tiles allowing limited-buffer deadlock conditions to occur and detecting and recovering from limited-buffer deadlock conditions.
2. The integrated circuit of claim 1 , wherein at least one of the networks that transmits data among the tiles preventing limited-buffer deadlock conditions is configured to provide separate buffer space in the memory coupled to the switches for data transmitted over different logical channels.
3. The integrated circuit of claim 1 , wherein at least one of the networks configured to transmit data among the tiles preventing limited-buffer deadlock conditions is configured to use credit based flow control.
4. The integrated circuit of claim 1 , wherein at least one of the networks configured to transmit data among the preventing limited-buffer deadlock conditions is configured to provide separate physical channels between tiles for request data and response data.
5. The integrated circuit of claim 1 , wherein at least two of the networks are configured to transmit data among the tiles detecting and recovering from limited-buffer deadlock conditions.
6. A method for transmitting data in an integrated circuit, the integrated circuit comprising a plurality of tiles, each tile comprising a processor, a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles, and memory coupled to the switch to buffer data transmitted among the tiles, with a plurality of networks among the tiles with each network comprising switches of the tiles and dedicated data paths directly connecting switches of neighboring tiles, the method comprising:
transmitting data over a first network among the tiles reserving sufficient buffer space in the memories coupled to the switches to prevent limited-buffer deadlock conditions from occurring; and
transmitting data over a second network among the tiles allowing limited-buffer deadlock conditions to occur and detecting and recovering from limited-buffer deadlock conditions;
the first network and the second network transferring data over data paths between neighboring tiles that include different sets of said data paths dedicated to the first network and to the second network to enable different networks to transfer data over the respective sets of data paths without sharing the same data paths between neighboring tiles.
7. The method of claim 6 , wherein at least one of the networks that transmits data among the tiles preventing limited-buffer deadlock conditions is configured to provide separate buffer space in the memory coupled to the switches for data transmitted over different logical channels.
8. The method of claim 6 , wherein preventing limited-buffer deadlock conditions includes using credit based flow control.
9. The method of claim 8 , wherein using credit based flow control comprises selecting an outstanding unacknowledged data credit limit to reserve sufficient buffer space in the memories coupled to the switches to prevent limited-buffer deadlock conditions.
10. The method of claim 6 , wherein preventing limited-buffer deadlock conditions includes providing separate physical channels between tiles for request data and response data.
11. The method of claim 6 , wherein recovering from limited-buffer deadlock conditions in the second network includes transmitting data among the tiles over the first network.
12. The integrated circuit of claim 1 , wherein each of the plurality of networks comprises a dimension-ordered wormhole routed network.
13. The integrated circuit of claim 1 , wherein the second network is configured to use buffer space in memory external to the tiles to recover from limited-buffer deadlock conditions.
14. The integrated circuit of claim 13 , wherein the external memory has cache on one or more of the tiles.
15. The integrated circuit of claim 13 , wherein the second network is configured to drain buffer space in the memories coupled to the switches to the external memory over the first network in response to detecting a limited-buffer deadlock condition.
16. The integrated circuit of claim 1 , wherein the second network is configured to detect limited-buffer deadlock conditions using a timer in each of multiple tiles that counts how many cycles data stays in buffer space in memories coupled to the switches without making forward progress.
17. The integrated circuit of claim 16 , wherein detecting a limited-buffer deadlock condition includes one or more of the counters reaching a predetermined threshold.
18. An apparatus comprising:
a plurality of tiles, each tile comprising
a processor,
a switch including switching circuitry to forward data words over data paths from other tiles to the processor and to switches of other tiles,
memory coupled to the switch to buffer data transmitted among the tiles, and
a timer configured to count how many cycles data stays in buffer space in the memory without making forward progress; and
external memory coupled to at least one of the tiles and external to the tiles;
a plurality of networks among the tiles with each network comprising switches of the tiles and dedicated data paths directly connecting switches of neighboring tiles, with data paths between neighboring tiles including different respective sets of said data paths dedicated to different networks to enable different networks to transfer data over the respective sets of data paths without sharing the same data paths between neighboring tiles, and
at least a first one of the networks configured to transmit data among the tiles reserving sufficient buffer space in the memories coupled to the switches to prevent limited-buffer deadlock conditions from occurring, and at least a second one of the networks configured to transmit data among the tiles allowing limited-buffer deadlock conditions to occur and detecting limited-buffer deadlock conditions using the timers and recovering from limited-buffer deadlock conditions using the external memory.
19. The apparatus of claim 18 , wherein the second network is configured to drain buffer space in the memories coupled to the switches to the external memory over the first network in response to detecting a limited-buffer deadlock condition.
20. The integrated circuit of claim 1 , wherein each tile includes multiple switches, where different switches are dedicated to different respective networks.