Global socket to socket cache coherence architecture
View Patent ↗A flexible, scalable server is described. The server includes plural server nodes each server node including processor cores and switching circuitry configured to couple the processor to a network among the cores with the plurality of cores implementing networking functions within the compute nodes wherein the plurality of cores networking capabilities allow the cores to connect to each other, and to offer a single interface to a network coupled to the server.
1. A method of maintaining cache coherency in a system comprising plural multi-core processor chips in plural sockets, the method comprising:
receiving at a memory controller a read request for a block of data, with the request received from a requesting processor in one of the plural sockets;
accessing an ownership directory that keeps track of which blocks are owned by the plural sockets to determine if the read request misses in the ownership directory, with the ownership directory tracking only cache blocks of data that are owned by one or more of the plural sockets;
when the read request misses in the ownership directory, activating a hybrid cache coherency protocol by:
marking the block of data with a shared status;
returning the block of data corresponding to the read request, with the shared status to the one of the plural sockets that has the requesting processor, without sending a snoop message to other sockets.
2. The method of claim 1 wherein the hybrid cache coherency does not track shared blocks.
3. The method of claim 1 wherein the ownership directory is in the memory controller, and when the status of the block of data is changed to shared, the method further comprises:
sending the block of data back to the memory controller.
4. The method of claim 1 wherein the ownership directory is located at the memory controller, and when the read request is for the block of data that missed in a cache that is a distributed cache and is at a cache level closest to memory.
5. The method of claim 1 wherein the protocol maintains cache coherence across multiple sockets and each block has a unique global home socket, where the global home socket is a memory bank location for the block of data.
6. A method of maintaining cache coherency in a system comprising plural multi-core processor chips in plural sockets, the method comprising:
receiving a write request from a requesting one of the plural sockets for a requested line at a memory controller;
accessing an ownership directory that keeps track of which blocks are owned by the plural sockets to determine if the write request misses in the ownership directory, with the ownership directory not tracking shared blocks of data and only tracking cache blocks of data that are owned by one or more of the plural sockets;
when the write request misses in the ownership directory,
sending snoops out to other sockets;
responding by a home socket that has the requested line for the write request to the requesting socket.
7. The method of claim 6 wherein each block of data is associated with a unique global socket home.
8. The method of claim 6 wherein the ownership directory is associative, with entries to record ownership of a cache block, when there is not a free entry, the memory controller provides an entry by revoking ownership of another block in the ownership directory.
9. The method of claim 6 wherein the ownership directory is located at the memory controller.
10. The method of claim 6 wherein when a socket of the plural sockets has an exclusive copy of the requested line, and an owned block is victimized from the socket that has the exclusive copy of the requested line, the requested line is sent back to the memory controller and removed from the ownership directory.
11. Apparatus comprising:
a memory controller for maintaining cache coherency, the controller configured for a system comprising plural multi-core processor chips in plural sockets, the apparatus configured to:
receive a read request from a requesting one of the plural sockets for a requested cache line;
access an ownership directory that keeps track of which blocks are owned by the plural sockets to determine if the read request hits or misses in the ownership directory, with the ownership directory tracking only cache lines of data that are owned by one or more of the plural sockets;
activate a hybrid cache coherency protocol either;
when the read request misses in the ownership directory by configuring the apparatus to:
mark the requested cache line with a shared status;
return the requested cache line corresponding to the read request without sending a snoop message to other sockets
or when the read request hits in the ownership directory by configuring the apparatus to:
change status of the requested cache line to a shared status;
remove from the ownership directory, a directory entry corresponding to the requested cache line having the changed shared status;
produce a specific socket ID corresponding to the multi-core processor chip socket that has the exclusive copy of the requested cache line; and
send a directed message to the specified socket to supply the requested cache line.
12. The apparatus of claim 11 configured to:
receive a write request at the memory controller;
access the ownership directory to determine if the write request hits or misses in the ownership directory;
when the write request misses in the ownership directory,
send snoops out to other sockets; and
respond by a home socket that has the requested line for the write request to the requesting socket;
or when the write hits in the ownership directory,
produce the specific socket ID that has the exclusive copy of the requested cache line; and
send a directed message to the specified socket to supply the requested cache line.
13. The apparatus of claim 11 , further configured to:
send the requested cache line back to the memory controller.
14. The apparatus of claim 11 wherein the ownership directory is located at the memory controller.
15. The apparatus of claim 11 wherein the protocol maintains cache coherence across multiple sockets and each cache line has a unique global home socket, where the global home socket is a memory bank location for the requested cache line.
16. Apparatus comprising:
a memory controller for maintaining cache coherency, the controller configured for a system comprising plural multi-core processor cores chips in plural sockets, the apparatus configured to:
receive from a requesting socket, a write request for a requested line at the memory controller;
access an ownership directory that keeps track of which blocks are owned by the plural sockets to determine if the write request hits or misses in the ownership directory, with the ownership directory tracking only cache blocks of data that are owned by a socket of the plural sockets;
when the write request misses in the ownership directory,
send snoops out to other sockets;
respond by a home socket that has the requested cache block of data for the write request to the requesting socket;
when the write hits in the ownership directory,
produce a specific socket ID that has the exclusive copy of the requested line; and
send a directed message to the specified socket.
17. The apparatus of claim 16 wherein the memory controller returns the requested cache block for read requests that miss the ownership directory and sends to specific sockets directed messages for read requests that hit in the ownership directory.
18. The apparatus of claim 16 wherein the ownership directory is associative, with entries to record ownership of a cache block, when there is not a free entry, the memory controller provides an entry by revoking ownership of another block in the ownership directory.
19. The apparatus of claim 16 wherein the ownership directory is located at the memory controller.
20. The apparatus of claim 16 wherein when an owned block is victimized from the socket that has the exclusive copy of the requested line, the requested line is sent back to the memory controller and removed from the ownership directory.
21. A method of maintaining cache coherency in a system comprising plural multi-core processor core chips in plural sockets, the method comprising:
receiving a read request at a memory controller, the request being for a block of data;
accessing an ownership directory that keeps track of which blocks are owned by the plural sockets to determine if the read request hits in the ownership directory, with the ownership directory tracking only cache blocks of data that are owned by a socket of the plural sockets;
when the read request hits in the ownership directory, activating a hybrid cache coherency protocol by:
changing status of the block of data to a shared status;
removing from the ownership directory, a directory entry corresponding to the requested block of data having the changed shared status;
producing a specific socket ID corresponding to the multi-core processor chip socket that has the exclusive copy of the requested block; and
sending a directed message to the specified socket to supply the requested block.
22. A method of maintaining cache coherency in a system comprising plural multi-core processor chips in plural sockets, the method comprising:
receiving a write request from a requesting one of the plural sockets for a requested line at a memory controller;
accessing an ownership directory that keeps track of which blocks are owned by the plural sockets to determine if the write request hits in the ownership directory, with the ownership directory not tracking shared blocks of data and only tracking cache blocks of data that are owned by one or more of the plural sockets;
when the write hits in the ownership directory,
producing a specific socket ID that has the exclusive copy of the requested line; and
sending a directed message to the specified socket.