Granted Patent B1

US 10,282,338 · App. 15/201,754 · Granted May 7, 2019

Abstract

Claims (37)

1. A multicore processor device, comprising:

a plurality of processor tiles, each tile comprising a processor core and a switch, and a routing arbiter that routes data packets;

a mesh interconnection network to interconnect switches of the processor cores, the mesh interconnection network having a plurality of dimensions in which an ordering of dimensions for routing data is configurable, the mesh interconnection network configurable to:

enable transfer of data among the processor cores;

bias routing in the mesh interconnection network according to a routing algorithm that selects a first dimension for routing over a second, different dimension for routing according to respective sizes of routing requests from the processor cores and respective sizes of responses from devices coupled to the processor core; and

wherein when the routing arbiter receives a packet, the routing arbiter queries a first dimension special purpose register that is programmed during boot time to determine the dimension ordering policy for routing.

2. The multicore processor device of claim 1 wherein the plurality of processor tiles are arranged in an array having a row of processor tiles, the apparatus further comprising:

a memory controller coupled to a half of the row of the processor array, with the multicore processor device configured to:

bias routing according to relatives sizes of data transmitted in response to memory reads that are data from a I/O device to a processor core than memory writes that are data from the processor core to the I/O device that is used to select the first dimension.

3. The multicore processor device of claim 1 , further comprising:

the first dimension special purpose register that is programmed during boot time.

4. The multicore processor device of claim 1 , wherein each packet has a destination in dimensional coordinates in a packet header portion of the packet.

5. The multicore processor device of claim 4 , wherein each routing arbiter has its own dimensional coordinates and the routing arbiter is configured to:

compare the packet destination dimensional coordinates with its own dimensional coordinates; and

route the packet based on the comparison and the information from the first dimension special purpose register.

6. The multicore processor device of claim 1 , further comprising:

multiple connections to the mesh interconnection network for peripheral devices, with a first one of the connections having more traffic sourced from the peripheral devices and a second one of the connections having more traffic, relative to the first connection, sent to the peripheral devices.

7. The multicore processor device of claim 6 wherein the plurality of processor tiles are arranged in an array having a row of processor tiles and at least some of the connections for peripheral devices are chosen according a processor array configuration of the array such that peripheral devices with heavy traffic are not connected to the first-dimension to reduce skin effect.

8. The multicore processor device of claim 1 wherein the interconnection network comprises N dimensions, N being an integer greater than 1.

9. An apparatus, comprising:

a multicore processor device, the multicore processor device comprising:

a plurality of processor tiles arranged in an array having a row of processor tiles, each tile comprising a processor core and a switch, and a routing arbiter that routes data packets;

a mesh interconnection network to interconnect switches of the processor cores, the mesh interconnection network having a plurality of dimensions in which an ordering of dimensions for routing data is configurable, the mesh interconnection network configurable to:

enable transfer of data among the processor cores;

bias routing in the mesh interconnection network according to a routing algorithm that selects a first dimension for routing over a second, different dimension for routing according to respective sizes of routing requests from the processor cores and respective sizes of responses from devices coupled to the processor cores;

wherein when the routing arbiter receives a packet, the routing arbiter queries a first dimension special purpose register that is programmed during boot time to determine the dimension ordering policy for routing;

a memory controller coupled to a half of the row of the processor array; and

memory coupled to the memory controller.

10. The apparatus of claim 9 wherein the array is a two-dimensional array of the processor tiles.

11. The apparatus of claim 10 wherein the array has a row of processor tiles, and the memory controller is coupled to a half of the row of the array, with the multicore processor device configured to:

bias routing according to relatives sizes of data transmitted in response to memory reads that are data from a I/O device to a processor core than memory writes that are data from the processor core to the I/O device that is used to select the first dimension.

12. The apparatus of claim 9 , further comprising:

the first dimension special purpose register that is programmed during boot time.

13. The apparatus of claim 9 wherein each packet has a destination in dimensional coordinates in a packet header portion of the packet.

14. The apparatus of claim 13 , wherein each routing arbiter has its own dimensional coordinates and the routing arbiter is configured to:

compare the packet destination dimensional coordinates with its own dimensional coordinates; and

route the packet based on the comparison and the information from the first dimension special purpose register.

Assignments (8)