Managing cache memory in a parallel processing environment
View Patent ↗An apparatus comprises a plurality of processor cores, each comprising a computation unit and a memory. The apparatus further comprises an interconnection network to transmit data among the processor cores. At least some of the memories are configured as a cache for memory external to the processor cores, and at least some of the processor cores are configured to transmit a message over the interconnection network to access a cache of another processor core.
1. An integrated circuit, comprising:
a plurality of tiles, each tile comprising:
a processor configured to send data resulting from processing an instruction to one of multiple destinations accessible within a register name space of the processor; and
switching circuitry including a switch to forward data received over data paths from other tiles to the processor, and to switches of other tiles, and to forward data received from the processor to other tiles, with the switching circuitry further including switch buffers that store data to be forwarded to switches of neighboring tiles, and data paths that transfer data to registers of neighboring tiles, and with at least a first one of destinations accessible within the register name space of the processor comprises a switch buffer addressed by a corresponding register specifier, and at least another one of the destinations comprises a register of a neighboring tile that is addressed by a corresponding register specifier.
2. The integrated circuit of claim 1 , wherein the instruction includes a register specifier that is a direct name identifying the register of the neighboring tile addressed by the register specifier.
3. The integrated circuit of claim 1 , wherein the instruction includes a register specifier that is a directional indicator that identifies the register of the neighboring tile coupled to a data path in a specified direction.
4. The integrated circuit of claim 3 , wherein the register specifier uses two bits of the instruction to encode one of four directions.
5. The integrated circuit of claim 1 , wherein, if a register specifier included in the instruction identifies a register of a neighboring tile, the data resulting from processing the instruction is sent to the register identified by the register specifier in a single hop.
6. The integrated circuit of claim 1 , wherein the processor is configured to process multiple streams of instructions.
7. The integrated circuit of claim 6 , wherein the processor comprises a Very Long Instruction Word (VLIW) processor and the instructions processed in respective functional units comprise subinstructions of a VLIW instruction.
8. The integrated circuit of claim 6 , wherein the processor comprises a superscalar processor and the instructions processed in respective functional units comprise instructions scheduled to issue concurrently.
9. The integrated circuit of claim 6 , wherein the processor comprises a multithreaded processor and the multiple streams of instructions comprise instructions from different threads.
10. The integrated circuit of claim 6 , wherein the processor is a pipelined processor and the switching circuitry is coupled to a plurality of stages of the pipeline.
11. The integrated circuit of claim 10 , wherein the switching circuitry is coupled to bypass paths that connect non-adjacent pipeline stages of the processor.
12. A method for processing instructions in an integrated circuit, the integrated circuit comprising a plurality of tiles, each tile comprising a switch, the method comprising:
sending data resulting from processing an instruction to one of multiple destinations accessible within a register name space of a processor of a tile; and
forwarding data received over data paths from other tiles to the processor, and to switches of other tiles, and forwarding data received from the processor to other tiles;
storing data to be forwarded to switches of neighboring tiles in switch buffers, and
transferring data to registers of neighboring tiles over the data paths to at least a first one of destinations accessible within the register name space of the processor to a switch buffer addressed by a corresponding register specifier, and at least another one of the destinations comprises a register of a neighboring tile addressed by a corresponding register specifier.
13. The method of claim 12 , wherein the register specifier comprises a direct name identifying the register of the neighboring tile addressed by the register specifier.
14. The method of claim 13 , further comprising sending the data resulting from processing the instruction to the register of the neighboring tile in a single hop.
15. The method of claim 12 , wherein the register specifier comprises a directional indicator that identifies the register of the neighboring tile coupled to a data path in a specified direction.
16. The method of claim 12 further comprising processing multiple streams of instructions.
17. The method of claim 16 further comprising processing the instructions in respective functional units that comprise subinstructions of a Very long Instruction Word (VLIW) instruction.
18. The method of claim 16 , further comprising processing the instructions in respective functional units of a superscalar processor, the functional units comprising instructions scheduled to issue concurrently.
19. The method of claim 16 , wherein the processor comprises a multithreaded processor and the multiple streams of instructions comprise instructions from different threads.
20. The method of claim 16 , wherein the processor is a pipelined processor and the switching circuitry is coupled to a plurality of stages of the pipeline.