IP Library Granted Patent US 9,135,215
Granted Patent B1
US 9,135,215 · App. 12/886,163 · Granted Sep 15, 2015

Route prediction in packet switched networks

Inventors: Ian Rudolf Bratt (Castle Rock, CO); Carl G. Ramey (Westborough, MA); Matthew Mattina (Worcester, MA)
Assignee: Tilera Corporation
G06F15/8023H04L47/823
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Quick Facts
Patent No.
US 9,135,215
App. No.
12/886,163
Granted
Sep 15, 2015
Kind
B1
Abstract

Communicating among nodes in a network includes: sending a packet from an origin node to a destination node over a route including plural nodes. At each node in the route, routing of the packet is initiated according to a predicted path concurrently with verifying the correctness of the predicted path based on analyzing route information in the packet. In response to results of verifying the correctness of the predicted path, the routing of the packet is completed according to the predicted path or initiating a routing of the packet according to an actual path based on the route information in the packet.

Claims (60)

1. A method for communicating among nodes in a network, the method comprising:

sending a packet from an origin node to a destination node over a route including plural nodes according to a routing scheme, by:

at each node in the route,

predicting a switch output port for a predicted path that is a most likely path for the packet according to the routing scheme;

initiating routing of the packet to the predicted output port by preparing to couple the packet from a switch input port to the predicted output port;

verifying concurrently with initiating the correctness of the predicted path based on analyzing route information in the packet; and

in response to results of verifying the correctness of the predicted path, completing the routing of the packet by coupling the packet to an output port of the switch according to the predicted path or initiating a routing of the packet according to an actual path based on the route information in the packet.

2. The method of claim 1 , wherein the predicted output port of the switch is related to the input port of the switch according to the predicted path.

3. The method of claim 2 , wherein preparing to couple the packet comprises providing control signals to a multiplexer in the switch of the node at which the packet arrives.

4. The method of claim 2 , wherein the network comprises a two-dimensional mesh network in which each of multiple nodes is connected to four neighboring nodes, and the predicted path is straight along one of the dimensions, and the predicted output port is related to the input port to route the packet over a straight path through the node at which the packet arrives.

5. The method of claim 4 , wherein the route including one or more nodes comprises a route including multiple nodes that is dimension ordered such that all hops along the route in a first dimension occur before any hops along the route in a second dimension occur.

6. The method of claim 1 , wherein the predicted path is stored in a given node and is used for multiple packets received at the given node.

7. The method of claim 1 , wherein the predicted path for a given packet received at a given node is chosen based on past performance of predicted paths chosen for previous packets received at the given node.

8. The method of claim 1 , wherein the nodes in the network comprise cores in a computing system, with each core comprising a processor and a switch.

9. The method of claim 1 , wherein verifying the correctness of the predicted path based on analyzing route information in the packet comprises calculating the actual path based on the route information in the packet and comparing the predicted path to the actual path.

10. The method of claim 1 , wherein verifying the correctness of the predicted path based on analyzing route information in the packet comprises a verification procedure that is faster than calculating the actual path.

11. The method of claim 1 , wherein the route information comprises an address of the destination node.

12. A computer-readable storage device storing a computer program for communicating among nodes in a computing system, the computer program including instructions for causing the computing system to:

send a packet from an origin node to a destination node over a route including plural nodes according to a routing scheme, by:

at each node in the route,

predict a switch output port for a predicted path that is a most likely path for the packet according to the routing scheme;

initiate routing of the packet to the predicted output port according to the predicted path;

verify concurrently with initiate routing, the correctness of the predicted path based on analyzing route information in the packet; and

in response to results of verifying the correctness of the predicted path, complete the routing of the packet according to the predicted path to the predicted output port or initiate a routing of the packet according to an actual path based on the route information in the packet.

13. A computing system, comprising:

a plurality of cores;

each of one or more of the cores comprising a switch; and

each of one or more of the cores comprising a processor, the processors configured to:

send a packet from an origin core to a destination core over a route including plural cores according to a routing scheme, by:

at each core in the route,

predict a switch output port for a predicted path that is a most likely path for the packet according to the routing scheme;

initiate routing of the packet to the predicted output port according to the predicted path;

verify concurrently with initiate routing, the correctness of the predicted path based on analyzing route information in the packet; and

in response to results of verifying the correctness of the predicted path, complete the routing of the packet to the predicted output port according to the predicted path or initiating a routing of the packet according to an actual path based on the route information in the packet.

14. The device of claim 12 , wherein instructions to initiate routing of the packet according to the predicted path comprise instructions to prepare to couple the packet from an input port of a switch in a node at which the packet arrives to a predicted output port of the switch that is related to the input port of the switch according to the predicted path.

15. The device of claim 14 , wherein instructions to prepare to couple the packet comprise instructions to provide control signals to a multiplexer in the switch of the node at which the packet arrives.

16. The device of claim 12 , wherein instructions to predict, predict a route over the network that comprises a two-dimensional mesh network in which each of multiple nodes is connected to four neighboring nodes, and the predicted path is straight along one of the dimensions, and the predicted output port is related to the input port to route the packet over a straight path through the node at which the packet arrives.

17. The device of claim 16 , wherein instructions to predict the route, predict for a route that includes one or more nodes comprising the route that includes multiple nodes that is dimension ordered such that all hops along the route in a first dimension occur before any hops along the route in a second dimension occur.

18. The device of claim 12 , wherein instructions cause the predicted path to be stored in a node for multiple packets received at the node.

19. The device of claim 12 , wherein the predicted path for a packet received at a node is determined based on past performance of predicted paths chosen for previous packets received at the node.

20. The device of claim 12 , wherein the instructions to predict, predict for nodes in the network, which comprise cores in a computing system, with each core comprising a processor and a switch.

21. The device of claim 12 , wherein the instructions to verify the correctness of the predicted path based on analyzing route information in the packet comprise instructions to:

calculate the actual path based on the route information in the packet; and

compare the predicted path to the actual path.

22. The device of claim 12 , wherein the instructions to verify the correctness of the predicted path based on analyzing route information in the packet comprise instructions to:

apply a verification procedure that is faster than calculating the actual path.

23. The device of claim 12 , wherein the route information comprises an address of the destination node.

24. The system of claim 13 , wherein instructions to initiate routing of the packet according to the predicted path comprise instructions to prepare to couple the packet from an input port of a switch in a node at which the packet arrives to a predicted output port of the switch that is related to the input port of the switch according to the predicted path.

25. The system of claim 13 , wherein instructions to prepare to couple the packet comprise instructions to provide control signals to a multiplexer in the switch of the node at which the packet arrives.

26. The system of claim 13 , wherein the processors are further configured to predict a route over a network that comprises a two-dimensional mesh network in which each of multiple nodes is connected to four neighboring nodes, and the predicted path is straight along one of the dimensions, and the predicted output port is related to the input port to route the packet over a straight path through the node at which the packet arrives.

27. The system of claim 26 , wherein the processors are further configured to predict the route, which includes one or more nodes comprising the route that includes multiple nodes that is dimension ordered such that all hops along the route in a first dimension occur before any hops along the route in a second dimension occur.

28. The system of claim 13 , wherein the processors are further configured to cause the predicted path to be stored in a node for multiple packets received at the node.

29. The system of claim 13 , wherein the predicted path for a packet received at a node is determined based on past performance of predicted paths chosen for previous packets received at the node.

30. The system of claim 13 , wherein the processors are further configured to predict, predict for nodes in the network, which comprise cores in a computing system, with each core comprising a processor and a switch.

31. The system of claim 13 , wherein the processors are further configured to verify the correctness of the predicted path based on analyzing route information in the packet by:

calculating the actual path based on the route information in the packet; and

comparing the predicted path to the actual path.

32. The system of claim 13 , wherein the processors are further configured to verify the correctness of the predicted path based on analyzing route information in the packet, by:

applying a verification procedure that is faster than calculating the actual path.

33. The system of claim 13 , wherein the route information comprises an address of the destination node.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL AT REEL/FRAME NO. 42962/0859 Recorded Jul 13, 2018
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MELLANOX TECHNOLOGIES, LTD.; MELLANOX TECHNOLOGIES TLV LTD.; MELLANOX TECHNOLOGIES SILICON PHOTONICS INC.
Reel/Frame 046551/0459 →
SECURITY INTEREST Recorded Jun 23, 2017
From: MELLANOX TECHNOLOGIES, LTD.; MELLANOX TECHNOLOGIES TLV LTD.; MELLANOX TECHNOLOGIES SILICON PHOTONICS INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 042962/0859 →
DIVIDEND DECLARATION FROM EZCHIP SEMICONDUCTOR INC. TO THE STOCKHOLDER OF RECORD ON 6/2/2015 (EZCHIP INC., A DELAWARE CORPORATION) Recorded Feb 16, 2017
From: EZCHIP SEMICONDUCTOR INC.
To: EZCHIP, INC.
Reel/Frame 041736/0013 →
PURCHASE AGREEMENT Recorded Feb 16, 2017
From: EZCHIP, INC.
To: EZCHIP SEMICONDUCTOR LTD.
Reel/Frame 041736/0151 →
MERGER Recorded Feb 16, 2017
From: EZCHIP TECHNOLOGIES LTD.
To: EZCHIP SEMICONDUCTOR LTD.
Reel/Frame 041736/0321 →
MERGER Recorded Feb 16, 2017
From: EZCHIP SEMICONDUCTOR LTD.
To: MELLANOX TECHNOLOGIES, LTD.
Reel/Frame 041870/0455 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 16, 2017
From: EZCHIP SEMICONDUCTOR LTD.
To: EZCHIP TECHNOLOGIES, LTD.
Reel/Frame 041736/0253 →
MERGER Recorded Feb 16, 2017
From: TILERA CORPORATION
To: EZCHIP SEMICONDUCTOR INC.
Reel/Frame 041735/0792 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 27, 2010
From: BRATT, IAN RUDOLF; RAMEY, CARL G.; MATTINA, MATTHEW
To: TILERA CORPORATION
Reel/Frame 025207/0886 →
Continuity (1)
Provisional Application 61244440 · Sep 21, 2009