Compiling code for parallel processing architectures based on control flow
View Patent ↗A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises forming subsets of instructions corresponding to different portions of a program, the subsets of instructions being related according to a control flow graph; for each of a first subset of branches in the control flow graph, scheduling a value of an associated branch condition to be broadcast to multiple computation units; for each of a second subset of branches in the control flow graph, representing each instruction dependent on an associated branch condition as a predicated instruction that includes a predicate for computing the associated branch condition; assigning each subset of instructions to one of the computation units for execution on the assigned computation unit; and converting at least some of the predicated instructions in a subset of instructions assigned to a given computation unit into unpredicated instructions that depend on a branch local to the given computation unit.
1. A method comprising:
receiving by a computer system an input program;
dividing by the computer system code of the input program for execution by a system comprising a plurality of computation units interconnected by an interconnection network into memory analysis regions, with a memory analysis region including at least one scheduling region that is fully contained in exactly one memory analysis region;
performing by the computer system memory analysis on each memory analysis region individually to partition static memory references into equivalence classes;
identifying by the computer system the equivalence classes and for a standalone program without cache coherence, further comprising:
determining whether the input program is standalone and has full control of its memory; and
performing global analysis on memory accesses to divide memory accesses and objects into the equivalency classes.
2. The method of claim 1 , wherein for architectures without cache coherence, the method further comprises:
inserting initialization and finalization codes for execution on entry and exit of each memory analysis region.
3. The method of claim 2 , wherein the codes perform copy-in and copy-out of data structures that are distributed across tiles of a target processor in the at least one scheduling region to insure that data in different equivalence classes do not map to the same cache line.
4. The method of claim 1 , wherein the memory accesses are read or write instructions and the objects are variables accessed by read or write instructions.
5. The method of claim 1 , wherein the equivalence classes are over the space of instructions that access memory objects and the memory objects that the instructions potentially point to.
6. The method of claim 1 , wherein the equivalence classes have at least one of the following properties that all accesses within an equivalence class only access objects in the same equivalence class and all objects within an equivalence class are only accessed by objects in the same class.
7. The method of claim 1 , wherein once the equivalence classes are identified, further comprising:
assign the memory accesses of different equivalence classes to different cores, so long as accesses in the same equivalence class are mapped to the same core.
8. The method of claim 7 , further comprising
assigning the objects in the different equivalence classes so that the objects do not share the same cache line.
9. The method of claim 7 , wherein equivalence classes are determined by:
performing pointer analysis on the input program; and
constructing a memory access graph where nodes represent either objects or memory accesses and an edge is always between a memory access and an object where the memory access may access the object.
10. A computer program product tangibly stored on a hardware computer readable medium, the computer program product for configuring a system comprising a plurality of computation units interconnected by an interconnection network for instruction level parallelism, the computer program product comprising instructions to cause a processor to:
receive an input program;
divide code of the input program for execution on the system comprising a plurality of computation units into memory analysis regions, with a memory analysis region including at least one scheduling region that is fully contained in exactly one memory analysis region;
perform memory analysis on each memory analysis region individually to partition static memory references into equivalence classes;
identify equivalence classes and for standalone programs without cache coherence, the computer program product executes instructions to:
determine whether the input program is standalone and has full control of its memory; and
perform global analysis on memory accesses to divide memory accesses and objects into the equivalency classes.
11. The computer program product of claim 10 , wherein for architectures without cache coherence, the computer program product further executes instructions to:
insert initialization and finalization codes for execution on entry and exit of each memory analysis region.
12. The computer program product of claim 11 wherein the codes perform copy-in and copy-out of data structures that are distributed across tiles of a target processor in the at least one scheduling region to insure that data in different equivalence classes do not map to the same cache line.
13. The computer program product of claim 10 , wherein the memory accesses are read or write instructions and the objects are variables accessed by read or write instructions.
14. The computer program product of claim 10 , wherein the equivalence classes are over the space of instructions that access memory objects and the memory objects that the instructions potentially point to.
15. The computer program product of claim 10 , wherein the equivalence classes have at least one of the following properties that all accesses within an equivalence class only access objects in the same equivalence class and all objects within an equivalence class are only accessed by objects in the same class.
16. The computer program product of claim 10 , further comprising instructions to:
assign the memory accesses of different equivalence classes to different cores, so long as accesses in the same equivalence class are mapped to the same core once the equivalence classes are identified.
17. The computer program product of claim 16 further comprising instructions to:
assign the objects in the different equivalence classes so that the objects do not share the same cache line.
18. The computer program product of claim 16 , further comprising instructions to:
perform pointer analysis on the input program; and
construct a memory access graph where nodes represent either objects or memory accesses and an edge is always between a memory access and an object where the memory access may access the object.
19. A system comprises:
one or more processors;
memory executing a computer program product for configuring a system comprising a plurality of computation units interconnected by an interconnection network for instruction level parallelism, the program comprising instructions to cause the one or more processors to:
receive an input program;
divide code of the input program, for execution on the system comprising a plurality of computation units, into memory analysis regions, with a memory analysis region including at least one scheduling region that is fully contained in exactly one memory analysis region;
perform memory analysis on each memory analysis region individually to partition static memory references into equivalence classes;
identify equivalence classes and for standalone programs without cache coherence, the computer program product executes instructions to:
determine whether the input program is standalone and has full control of its memory, and
perform global analysis on memory accesses to divide memory accesses and objects into the equivalency classes.
20. The system of claim 19 , wherein for architectures without cache coherence, the computer program product further executes instructions to:
insert initialization and finalization codes for execution on entry and exit of each memory analysis region.
21. The system of claim 19 , wherein the codes perform copy-in and copy-out of data structures that are distributed across tiles of a target processor in the at least one scheduling region to insure that data in different equivalence classes do not map to the same cache line.
22. The system of claim 19 wherein the memory accesses are read or write instructions and the objects are variables accessed by read or write instructions.
23. The system of claim 19 wherein the equivalence classes are over the space of instructions that access memory objects and the memory objects that the instructions potentially point to.
24. The system of claim 19 , wherein the equivalence classes have at least one of the following properties that all accesses within an equivalence class only access objects in the same equivalence class and all objects within an equivalence class are only accessed by objects in the same class.
25. The system of claim 19 wherein the computer program, further comprises instructions to:
assign the memory accesses of different equivalence classes to different cores, so long as accesses in the same equivalence class are mapped to the same core once the equivalence classes are identified.
26. The system of claim 25 wherein the computer program, further comprises instructions to:
assign the objects in the different equivalence classes so that the objects do not share the same cache line.
27. The system of claim 25 wherein the computer program, further comprises instructions to:
perform pointer analysis on the input program; and
construct a memory access graph where nodes represent either objects or memory accesses and an edge is always between a memory access and an object where the memory access may access the object.