Caching in multicore and multiprocessor architectures
View Patent ↗A multicore processor comprises a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; one or more memory interfaces providing memory access paths from the cache memories to a main memory; and one or more directory controllers for respective portions of the main memory, each associated with corresponding storage for directory state. Each corresponding storage provides space for maintaining directory state for each memory line that is indicated as stored in at least one of the cache memories such that the space for maintaining directory state is independent of the size of the main memory.
1. A multicore processor comprising:
a plurality of cache memories;
a plurality of processor cores, each associated with one of the cache memories;
one or more memory interfaces providing memory access paths from the cache memories to a main memory; and
one or more directory controllers for respective portions of the main memory, each associated with corresponding storage for directory state;
with each corresponding storage providing space for maintaining directory state for each memory line that is indicated as stored in at least one of the cache memories such that the space for maintaining directory state is independent of the size of the main memory.
2. The processor of claim 1 wherein each corresponding storage provides space for maintaining directory state for each memory line that is indicated as stored in at least one of the cache memories and stores shared data.
3. The processor of claim 2 wherein each directory controller determines that a memory line stores shared data based on at least one of information in a message from the cache, the address of the memory line, information in a memory map, or a mode bit.
4. The processor of claim 1 wherein each directory controller associated with a corresponding storage filters out directory state for memory lines that are not stored in at least one of the cache memories.
5. The processor of claim 1 wherein each corresponding storage provides space for maintaining directory state for each memory line that is actually stored in at least one of the cache memories.
6. The processor of claim 1 wherein each directory controller associated with a corresponding storage evicts a directory entry from the storage in response to the storage becoming full.
7. The processor of claim 6 wherein the directory controller sends a message over an interconnection network connecting the processor cores to invalidate corresponding cache lines associated with the directory entry before evicting the directory entry from the storage.
8. The processor of claim 6 wherein the directory controller saves the directory entry in the main memory upon evicting the directory entry from the storage.
9. The processor of claim 8 wherein, in response to a request associated with the directory entry, the directory controller queries the main memory to obtain the directory entry if that entry is not present in the storage.
10. The processor of claim 1 wherein the processor cores are interconnected over a network that includes at least one of: a bus, a ring, a mesh, a torus, a 3D cube, or a hypercube.
11. The processor of claim 1 further comprising one or more input/output modules configured to couple data between a cache memory and an input/output interface.
12. A method for managing cache memories associated with respective processor cores in a multicore processor that includes one or more memory interfaces providing memory access paths from the cache memories to a main memory, the method comprising:
operating one or more directory controllers for respective portions of the main memory; and
providing space for maintaining directory state associated with the directory controllers for each memory line that is indicated as stored in at least one of the cache memories such that the space for maintaining directory state is independent of the size of the main memory.
13. A multicore processor comprising:
a plurality of cache memories;
a plurality of processor cores, each associated with one of the cache memories;
one or more memory interfaces providing memory access paths from the cache memories to a main memory; and
one or more directory controllers for respective portions of the main memory, each associated with corresponding storage for directory state;
with each of at least some of the directory controllers configured to maintain a common directory entry in the storage for storing directory state for multiple cache lines, and with the common directory entry storing directory state for cache lines whose addresses have one or more bits at specified positions in common.
14. The processor of claim 13 wherein the bits at the specified positions comprise low order bits.
15. The processor of claim 13 wherein the common directory entry stores directory state for the multiple cache lines and stores pointers to storage locations of the cache lines.
16. The processor of claim 15 wherein the directory controllers are configured to invalidate the cache lines stored in the storage locations in response to any of the cache lines being written.
17. The processor of claim 13 wherein the number of cache lines for which directory state is stored in the common directory entry is configurable based on information stored in the processor cores or the memory interfaces.
18. The processor of claim 13 wherein the processor cores are interconnected over a network that includes at least one of: a bus, a ring, a mesh, a torus, a 3D cube, or a hypercube.
19. The processor of claim 13 further comprising one or more input/output modules configured to couple data between a cache memory and an input/output interface.
20. A method for managing cache memories associated with respective processor cores in a multicore processor that includes one or more memory interfaces providing memory access paths from the cache memories to a main memory, the method comprising:
operating one or more directory controllers for respective portions of the main memory;
maintaining directory state associated with the directory controllers including maintaining a common directory entry for multiple cache lines; and
storing in the common directory entry directory state for cache lines whose addresses have one or more bits at specified positions in common.
21. A multicore processor comprising:
a plurality of cache memories;
a plurality of processor cores, each associated with one of the cache memories;
one or more memory interfaces providing memory access paths from the cache memories to a main memory; and
one or more directory controllers for respective portions of the main memory, each associated with corresponding storage for directory state;
with each of at least some of the directory controllers configured to maintain a common directory entry in the storage for storing directory state for multiple cache lines, and with the common directory entry storing directory state for the multiple cache lines and storing pointers to storage locations of the cache lines.
22. The processor of claim 21 wherein the common directory entry stores directory state for cache lines whose addresses have one or more bits at specified positions in common, and the bits at the specified positions comprise low order bits.
23. The processor of claim 21 wherein the directory controllers are configured to invalidate the cache lines stored in the storage locations in response to any of the cache lines being written.
24. The processor of claim 21 wherein the number of cache lines for which directory state is stored in the common directory entry is configurable based on information stored in the processor cores or the memory interfaces.
25. The processor of claim 21 wherein the processor cores are interconnected over a network that includes at least one of: a bus, a ring, a mesh, a torus, a 3D cube, or a hypercube.
26. The processor of claim 21 further comprising one or more input/output modules configured to couple data between a cache memory and an input/output interface.
27. A method for managing cache memories associated with respective processor cores in a multicore processor that includes one or more memory interfaces providing memory access paths from the cache memories to a main memory, the method comprising:
operating one or more directory controllers for respective portions of the main memory;
maintaining directory state associated with the directory controllers including maintaining a common directory entry for multiple cache lines; and
storing in the common directory entry directory state for the multiple cache lines and storing pointers to storage locations of the cache lines.
28. A multicore processor comprising:
a plurality of cache memories;
a plurality of processor cores, each associated with one of the cache memories;
one or more memory interfaces providing memory access paths from the cache memories to a main memory; and
one or more directory controllers for respective portions of the main memory, each associated with corresponding storage for directory state;
with each of at least some of the directory controllers configured to maintain a common directory entry in the storage for storing directory state for multiple cache lines, and with the number of cache lines for which directory state is stored in the common directory entry being configurable based on information stored in the processor cores or the memory interfaces.
29. The processor of claim 28 wherein the common directory entry stores directory state for cache lines whose addresses have one or more bits at specified positions in common, and the bits at the specified positions comprise low order bits.
30. The processor of claim 28 wherein the common directory entry stores directory state for the multiple cache lines and stores pointers to storage locations of the cache lines, and the directory controllers are configured to invalidate the cache lines stored in the storage locations in response to any of the cache lines being written.
31. The processor of claim 28 wherein the processor cores are interconnected over a network that includes at least one of: a bus, a ring, a mesh, a torus, a 3D cube, or a hypercube.
32. The processor of claim 28 further comprising one or more input/output modules configured to couple data between a cache memory and an input/output interface.
33. A method for managing cache memories associated with respective processor cores in a multicore processor that includes one or more memory interfaces providing memory access paths from the cache memories to a main memory, the method comprising:
operating one or more directory controllers for respective portions of the main memory;
maintaining directory state associated with the directory controllers including maintaining a common directory entry for multiple cache lines; and
configuring the number of cache lines for which directory state is stored in the common directory entry based on information stored in the processor cores or the memory interfaces.