IP Library Granted Patent US 9,479,431
Granted Patent B1
US 9,479,431 · App. 14/854,286 · Granted Oct 25, 2016

Route prediction in packet switched networks

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Quick Facts
Patent No.
US 9,479,431
App. No.
14/854,286
Granted
Oct 25, 2016
Kind
B1
Abstract

Communicating among nodes in a network includes: sending a packet from an origin node to a destination node over a route including plural nodes. At each node in the route, routing of the packet is initiated according to a predicted path concurrently with verifying the correctness of the predicted path based on analyzing route information in the packet. In response to results of verifying the correctness of the predicted path, the routing of the packet is completed according to the predicted path or initiating a routing of the packet according to an actual path based on the route information in the packet.

Claims (35)

1. A method for communicating among nodes in a network, the method comprising:

sending a packet from an origin node to a destination node over a route that includes a plurality of nodes including the origin node and the destination plural node;

determining at a first node in the route, a predicted path to a subsequent node in the route;

verifying correctness of the predicted path based on analyzing route information in the packet;

initiating routing of the packet according to the predicted path by configuring an output multiplexer of the first node to speculatively select an input port from which to route the packet, concurrently with verifying the correctness of the predicted path based on analyzing route information in the packet; and

in response to results of verifying the correctness of the predicted path, either completing the routing of the packet according to the predicted path, when the path was correctly predicted or initiating a routing of the packet according to an actual path based on the route information in the packet when the path was not correctly predicted.

2. The method of claim 1 , wherein initiating routing of the packet according to the predicted path comprises preparing the multiplexer to couple the packet from an input port of a switch in the first node at which the packet arrives to a predicted output port of the switch that is related to the input port of the switch according to the predicted path.

3. The method of claim 2 , wherein preparing to couple the packet comprises providing control signals to the multiplexer in the switch of the first node at which the packet arrives.

4. The method of claim 2 , wherein the network comprises a two-dimensional mesh network in which each of multiple nodes is connected to four neighboring nodes, and the predicted path is straight along one of the dimensions, and the predicted output port is related to the input port to route the packet over a straight path through the first node at which the packet arrives to the subsequent node.

5. The method of claim 4 , wherein the route including one or more nodes comprises a route including multiple nodes that is dimension ordered such that all hops along the route in a first dimension occur before any hops along the route in a second dimension occur.

6. The method of claim 1 , wherein the predicted path is stored in a stage of the first a given node and is used for multiple packets received at the first given node.

7. The method of claim 1 , wherein the predicted path for the a given packet received at the first a given node is chosen based on past performance of predicted paths chosen for previous packets received at the first given node.

8. The method of claim 1 , wherein the nodes in the network comprise cores in a computing system, with each core comprising a processor and a switch.

9. The method of claim 1 , wherein verifying the correctness of the predicted path based on analyzing route information in the packet comprises:

calculating by the node the actual path based on the route information in the packet; and

comparing by the node the predicted path to the calculated actual path.

10. The method of claim 1 , wherein the method further comprises:

invalidating by the node the predicted path when verifying the correctness of the predicted path fails; and

preventing the packet from leaving the node until the actual route is computed based on analyzing route information in the packet comprises a verification procedure that is faster than calculating the actual path.

11. The method of claim 1 , wherein the route information comprises an address of the destination node.

12. A computer-readable hardware storage device storing a computer program for communicating among nodes in a computing system, the computer program including instructions for causing the computing system to:

send a packet from an origin node to a destination node over a route that includes a plurality of nodes including the origin node and the destination plural node;

determine at a first node in the route, a predicted path to a subsequent node in the route;

verify correctness of the predicted path based on analyzing route information in the packet;

initiate routing of the packet according to the predicted path by configuring an output multiplexer of the first node to speculatively select an input port from which to route the packet, concurrently with verifying the correctness of the predicted path based on analyzing route information in the packet; and

in response to results of verifying the correctness of the predicted path, either complete the routing of the packet according to the predicted path, when the path was correctly predicted or initiating a routing of the packet according to an actual path based on the route information in the packet when the path was not correctly predicted.

13. A computing system, comprising:

a plurality of cores;

each of one or more of the cores comprising a switch; and

each of one or more of the cores comprising a processor, the processors configured to:

send a packet from an origin core to a destination core over a route that includes a plurality of cores including the origin core and the destination plural core;

determine at a first core in the route, a predicted path to a subsequent core in the route;

verify correctness of the predicted path based on analyzing route information in the packet;

initiating initiate routing route of the packet according to the predicted path by configuring an output multiplexer of the first core to speculatively select an input port from which to route the packet, concurrently with verifying the correctness of the predicted path; and

in response to results of verifying the correctness of the predicted path, either complete the routing of the packet according to the predicted path, when the path was correctly predicted or initiating a routing of the packet according to an actual path based on the route information in the packet when the path was not correctly predicted.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL AT REEL/FRAME NO. 42962/0859 Recorded Jul 13, 2018
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MELLANOX TECHNOLOGIES, LTD.; MELLANOX TECHNOLOGIES TLV LTD.; MELLANOX TECHNOLOGIES SILICON PHOTONICS INC.
Reel/Frame 046551/0459 →
SECURITY INTEREST Recorded Jun 23, 2017
From: MELLANOX TECHNOLOGIES, LTD.; MELLANOX TECHNOLOGIES TLV LTD.; MELLANOX TECHNOLOGIES SILICON PHOTONICS INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 042962/0859 →
DIVIDEND DECLARATION FROM EZCHIP SEMICONDUCTOR INC. TO THE STOCKHOLDER OF RECORD ON 6/2/2015 (EZCHIP INC., A DELAWARE CORPORATION) Recorded Feb 16, 2017
From: EZCHIP SEMICONDUCTOR INC.
To: EZCHIP, INC.
Reel/Frame 041736/0013 →
PURCHASE AGREEMENT Recorded Feb 16, 2017
From: EZCHIP, INC.
To: EZCHIP SEMICONDUCTOR LTD.
Reel/Frame 041736/0151 →
MERGER Recorded Feb 16, 2017
From: EZCHIP TECHNOLOGIES LTD.
To: EZCHIP SEMICONDUCTOR LTD.
Reel/Frame 041736/0321 →
MERGER Recorded Feb 16, 2017
From: EZCHIP SEMICONDUCTOR LTD.
To: MELLANOX TECHNOLOGIES, LTD.
Reel/Frame 041870/0455 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 16, 2017
From: EZCHIP SEMICONDUCTOR LTD.
To: EZCHIP TECHNOLOGIES, LTD.
Reel/Frame 041736/0253 →
MERGER Recorded Feb 16, 2017
From: TILERA CORPORATION
To: EZCHIP SEMICONDUCTOR INC.
Reel/Frame 041735/0792 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 19, 2016
From: BRATT, IAN RUDOLF; RAMEY, CARL G.; MATTINA, MATTHEW
To: EZCHIP TECHNOLOGIES LTD.
Reel/Frame 039774/0983 →