Managing memory access in a parallel processing environment
View Patent ↗An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles. The integrated circuit further comprises one or more memory interface modules including circuitry to access an external memory, each memory interface module coupled to a switch of at least one tile. At least some of the tiles are configured to send a message to a memory interface module to determine whether previous memory transactions associated with a tile have been completed.
1. An integrated circuit, comprising:
a plurality of tiles, each tile comprising
a processor, and
a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles; and
one or more memory interface modules including circuitry to access an external memory, each memory interface module coupled to a switch of at least one tile;
with at least some of the tiles configured to send a message to a memory interface module to determine whether previous memory transactions associated with a tile have been completed, and configured to send the message to the memory interface module in response to executing a predetermined instruction in the processor; and
the tiles are configured to ensure that previous memory transactions associated with instructions processed before the predetermined instruction are completed before memory transactions associated with instructions processed after the predetermined instruction are initiated.
2. The integrated circuit of claim 1 , wherein the memory interface modules comprise memory controllers.
3. The integrated circuit of claim 1 , wherein the tile with which the previous memory transactions are associated comprises the tile sending the message.
4. The integrated circuit of claim 1 , wherein the tile with which the previous memory transactions are associated comprises a different tile from the tile sending the message.
5. The integrated circuit of claim 1 , wherein the previous memory transactions associated with the tile comprise memory load and/or store requests from a module in the tile.
6. The integrated circuit of claim 1 , wherein the previous memory transactions associated with the tile comprise memory load and/or store requests from a device coupled to the tile.
7. The integrated circuit of claim 1 , wherein the previous memory transactions associated with the tile comprise memory load and/or store requests to a designated memory interface module.
8. An integrated circuit, comprising:
a plurality of tiles, each tile comprising
a processor, and
a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles; and
one or more memory interface modules including circuitry to access an external memory, each memory interface module coupled to a switch of at least one tile;
with at least some of the tiles configured to send a message to a memory interface module to determine whether previous memory transactions associated with a tile have been completed, and configured to send the message to the memory interface module in response to executing a predetermined instruction in the processor; and
the tiles are configured to ensure that previous memory transactions to a predetermined memory interface module are completed before instructions processed after the predetermined instruction are executed.
9. The integrated circuit of claim 8 , wherein the memory interface modules comprise memory controllers.
10. The integrated circuit of claim 8 , wherein the tile with which the previous memory transactions are associated comprises the tile sending the message.
11. The integrated circuit of claim 8 , wherein the tile with which the previous memory transactions are associated comprises a different tile from the tile sending the message.
12. The integrated circuit of claim 8 , wherein the previous memory transactions associated with the tile comprise memory load and/or store requests from a module in the tile.
13. The integrated circuit of claim 8 , wherein the previous memory transactions associated with the tile comprise memory load and/or store requests from a device coupled to the tile.
14. The integrated circuit of claim 8 , wherein the previous memory transactions associated with the tile comprise memory load and/or store requests to a designated memory interface module.
15. An integrated circuit, comprising:
a plurality of tiles, each tile comprising
a processor, and
a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles; and
one or more memory interface modules including circuitry to access an external memory, each memory interface module coupled to a switch of at least one tile;
with at least some of the tiles configured to send a message to a memory interface module to determine whether previous memory transactions associated with a tile have been completed, and configured to send the message to the memory interface module in response to executing a predetermined instruction in the processor; and
the tiles are configured to ensure that previous memory transactions from a predetermined tile are completed before instructions processed after the predetermined instruction are executed.
16. The integrated circuit of claim 15 , wherein the memory interface modules comprise memory controllers.
17. The integrated circuit of claim 15 , wherein the tile with which the previous memory transactions are associated comprises the tile sending the message.
18. The integrated circuit of claim 15 , wherein the tile with which the previous memory transactions are associated comprises a different tile from the tile sending the message.
19. The integrated circuit of claim 15 , wherein the previous memory transactions associated with the tile comprise memory load and/or store requests from a module in the tile.
20. The integrated circuit of claim 15 , wherein the previous memory transactions associated with the tile comprise memory load and/or store requests from a device coupled to the tile.
21. The integrated circuit of claim 15 , wherein the previous memory transactions associated with the tile comprise memory load and/or store requests to a designated memory interface module.
22. An integrated circuit, comprising:
a plurality of tiles, each tile comprising
a processor, and
a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles; and
one or more memory interface modules including circuitry to access an external memory, each memory interface module coupled to a switch of at least one tile;
with at least some of the tiles configured to send a message to a memory interface module to determine whether previous memory transactions associated with a tile have been completed, and configured to send the message to the memory interface module in response to executing a predetermined instruction in the processor; and
the tiles are configured to execute the predetermined instruction before sending data from an output port of the switch.
23. The integrated circuit of claim 22 , wherein the memory interface modules comprise memory controllers.
24. The integrated circuit of claim 22 , wherein the tile with which the previous memory transactions are associated comprises the tile sending the message.
25. The integrated circuit of claim 22 , wherein the tile with which the previous memory transactions are associated comprises a different tile from the tile sending the message.
26. The integrated circuit of claim 22 , wherein the previous memory transactions associated with the tile comprise memory load and/or store requests from a module in the tile.
27. The integrated circuit of claim 22 , wherein the previous memory transactions associated with the tile comprise memory load and/or store requests from a device coupled to the tile.
28. The integrated circuit of claim 22 , wherein the previous memory transactions associated with the tile comprise memory load and/or store requests to a designated memory interface module.
29. An integrated circuit, comprising:
a plurality of tiles, each tile comprising
a processor; and
a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles;
with at least some of the tiles configured to transmit a message that identifies a synchronization operation to be performed with respect to a memory, and the synchronization operation comprises reading stored data from an address in the memory and writing a data value included in the message into the memory address after the stored data is read, where reading the stored data and writing the data value occur atomically.
30. The integrated circuit of claim 29 , wherein the memory comprises an external memory coupled to at least one of the tiles by a memory controller.
31. The integrated circuit of claim 29 , wherein the memory comprises a memory in a tile.
32. The integrated circuit of claim 31 , wherein at least a portion of the memory is configured as a cache for memory external to the tiles.
33. The integrated circuit of claim 32 , wherein the message is sent to the external memory in response to a cache miss.
34. An integrated circuit, comprising:
a plurality of tiles, each tile comprising
a processor, and
a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles; and
one or more memory interface modules including circuitry to access an external memory, each memory interface module coupled to a switch of at least one tile;
with at least some of the tiles configured to send a message to a memory interface module to determine whether previous memory transactions associated with a tile have been completed; and
with at least one tile configured to send a message to a memory interface module to determine whether previous memory transactions associated with a tile have been completed is further configured to maintain a count of outstanding memory transactions.
35. The integrated circuit of claim 34 , wherein the at least one tile is configured to receive an acknowledgement message from the memory interface module for each outstanding memory transaction to indicate successful completion of the corresponding memory transaction.
36. The integrated circuit of claim 35 , wherein the acknowledgement message from the memory interface module comprises a returned data value associated with the memory transaction.
37. An integrated circuit, comprising:
a plurality of tiles, each tile comprising
a processor; and
a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles;
with at least some of the tiles configured to transmit a message that identifies a synchronization operation to be performed with respect to a memory
with the message that identifies a synchronization operation to be performed with respect to a memory being sent from a requesting tile over the network to a target tile.
38. The integrated circuit of claim 37 , wherein the target tile is configured to determine the identified synchronization operation based on the message, and perform an atomic sequence of memory operations associated with the synchronization operation on a local memory.
39. The integrated circuit of claim 38 , wherein the target tile is configured to send a result of the atomic sequence of memory operations in a message to the requesting tile.
40. A method for processing instructions in an integrated circuit, the integrated circuit comprising a plurality of tiles, each tile comprising a processor and a switch, the method comprising:
processing instructions in a processor of a tile;
forwarding data received over data paths from other tiles to the processor and to switches of other tiles, and forwarding data received from the processor to switches of other tiles;
accessing an external memory through a memory interface module coupled to a switch of at least one tile;
sending a message to the memory interface module to determine whether previous memory transactions associated with a tile have been completed, in response to executing a predetermined instruction in the processor; and
ensuring that previous memory transactions associated with instructions processed before the predetermined instruction are completed before memory transactions associated with instructions processed after the predetermined instruction are initiated.
41. A method for processing instructions in an integrated circuit, the integrated circuit comprising a plurality of tiles, each tile comprising a processor and a switch, the method comprising:
processing instructions in a processor of a tile;
forwarding data received over data paths from other tiles to the processor and to switches of other tiles, and forwarding data received from the processor to switches of other tiles; and
transmitting a message from the tile that identifies a synchronization operation to be performed with respect to a memory, with the message that identifies a synchronization operation to be performed with respect to a memory being sent from a requesting tile over the network to a target tile.
42. A method for processing instructions in an integrated circuit, the integrated circuit comprising a plurality of tiles, each tile comprising a processor and a switch, the method comprising:
processing instructions in a processor of a tile;
forwarding data received over data paths from other tiles to the processor and to switches of other tiles, and forwarding data received from the processor to switches of other tiles;
accessing an external memory through a memory interface module coupled to a switch of at least one tile;
sending a message to the memory interface module to determine whether previous memory transactions associated with a tile have been completed, in response to executing a predetermined instruction in the processor; and
ensuring that previous memory transactions to a predetermined memory interface module are completed before instructions processed after the predetermined instruction are executed.
43. A method for processing instructions in an integrated circuit, the integrated circuit comprising a plurality of tiles, each tile comprising a processor and a switch, the method comprising:
processing instructions in a processor of a tile;
forwarding data received over data paths from other tiles to the processor and to switches of other tiles, and forwarding data received from the processor to switches of other tiles;
accessing an external memory through a memory interface module coupled to a switch of at least one tile;
sending a message to the memory interface module to determine whether previous memory transactions associated with a tile have been completed, in response to executing a predetermined instruction in the processor; and
ensuring that previous memory transactions from a predetermined tile are completed before instructions processed after the predetermined instruction are executed.
44. A method for processing instructions in an integrated circuit, the integrated circuit comprising a plurality of tiles, each tile comprising a processor and a switch, the method comprising:
processing instructions in a processor of a tile;
forwarding data received over data paths from other tiles to the processor and to switches of other tiles, and forwarding data received from the processor to switches of other tiles;
accessing an external memory through a memory interface module coupled to a switch of at least one tile;
sending a message to the memory interface module to determine whether previous memory transactions associated with a tile have been completed, in response to executing a predetermined instruction in the processor; and
executing the predetermined instruction before sending data from an output port of the switch.