Managing cache memory in a parallel processing environment
View Patent ↗An apparatus comprises a plurality of processor cores, each comprising a computation unit and a memory. The apparatus further comprises an interconnection network to transmit data among the processor cores. At least some of the memories are configured as a cache for memory external to the processor cores, and at least some of the processor cores are configured to transmit a message over the interconnection network to access a cache of another processor core.
1. An apparatus, comprising:
a plurality of processor cores, each comprising a computation unit and a memory; and
an interconnection network to transmit data among the processor cores;
with two or more of the memories in respective cores having a portion thereof configured as a cache for storing cached data from a memory that is external to the processor cores, and with one or more of the processor cores configured to transmit a message over the interconnection network to another one of the processor cores, in response to a request to access cached data, to access the cached data stored in the portion of the memory configured as a cache in the other processor core receiving the message, with the processor core that transmits the message configured to maintain information sufficient to identify a cache location to be accessed and is not required to access directory information stored external to the processor core to identify the cache location, with the processor core that transmits the message further including a buffer to store the maintained information.
2. The apparatus of claim 1 , wherein a processor core is configured to determine whether to access a local cache or to transmit the message to access the cache of the other processor core based on information stored in the buffer.
3. The apparatus of claim 2 , wherein the processor core is configured to transmit the message to access the cache of the other processor core without requiring access to the local cache.
4. The apparatus of claim 1 , wherein the processor core that transmits the message is configured to transmit the message to access the cache of the other processor core in response to a cache miss associated with a local cache.
5. The apparatus of claim 1 , wherein the processor core that transmits the message is configured to write data into a local cache and include the data in the message to be written into the cache of the other processor core.
6. The apparatus of claim 5 , wherein the processor core that transmits the message is configured to write the data into the local cache without marking the data as dirty.
7. The apparatus of claim 1 , wherein the processor core receiving the message is configured to access data associated with the message in a memory external to the processor cores upon a cache miss.
8. The apparatus of claim 1 , wherein one or more of the processor cores are configured to operate in a mode in which valid data from a given external memory address is stored in at most one of the caches.
9. The apparatus of claim 1 , wherein one or more of the processor cores are configured to operate in a mode in which valid data from a given external memory address is coherently updated between a plurality of the caches.
10. The apparatus of claim 1 , wherein one or more of the processor cores are configured to operate in
a first mode in which valid data from a given external memory address is stored in at most one of the caches; and
a second mode in which valid data from a given external memory address is coherently updated in a plurality of the caches.
11. The apparatus of claim 10 , wherein one or more of the processor cores are configured to switch between the first and second modes of operation during runtime.
12. The apparatus of claim 10 , wherein one or more of the processor cores are configured to switch between the first and second modes of operation based on history of memory access in the processor cores.
13. The apparatus of claim 1 , wherein the message transmitted by a first processor core to a second processor core includes a request to load data from the cache of the second processor core to the first processor core.
14. The apparatus of claim 13 , wherein the message transmitted by a first processor core to a second processor core includes a request to load a cache line from the cache of the second processor core to the cache of the first processor core.
15. The apparatus of claim 13 , wherein the first processor core is further configured to store the received data from the cache of the second processor core in the cache of the first processor core.
16. The apparatus of claim 13 , wherein the first processor core is further configured to store the received data from the cache of the second processor core in a memory location in the first processor core outside the cache of the first processor core.
17. The apparatus of claim 13 , wherein the second processor core is configured to mark the copy of the data that remains in the cache of the second processor core as dirty.
18. The apparatus of claim 17 , wherein the second processor core is configured to mark the copy of the data as dirty in response to granting the request to load the data.
19. The apparatus of claim 17 , wherein the second processor core is configured to mark the copy of the data as dirty in response to the data being stored in the cache of the first processor core.
20. The apparatus of claim 1 , wherein the message includes a request to access data classified as read-only data.
21. The apparatus of claim 1 , wherein the message includes a request to access instruction data.
22. The apparatus of claim 1 , wherein the message transmitted by a first processor core to a second processor core includes a request to store data from the cache of the first processor core in the cache of the second processor core.
23. The apparatus of claim 1 , wherein each of the plurality of processor cores corresponds to a tile on an integrated circuit, each tile comprising:
a computation unit; and
a switch including switching circuitry to forward data received over data paths of the interconnection network from other tiles to the computation unit and to switches of other tiles, and to forward data received from the computation unit to switches of other tiles.
24. The apparatus of claim 1 , wherein the interconnection network comprises a mesh network, a ring network, a bus network, or a fully connected crossbar fabric.
25. An apparatus, comprising:
a plurality of processor cores, each comprising a computation unit and a memory; and
an interconnection network to transmit data among the processor cores;
with two or more of the memories in respective cores having a portion thereof configured as a cache for storing cached data from a memory that is external to the processor cores, and with one or more of the processor cores configured to transmit a message over the interconnection network to another one of the processor cores, in response to a request to access cached data, to access the cached data stored in the portion of the memory configured as a cache in the other processor core receiving the message, with the processor core that transmits the message being configured to maintain information sufficient to identify a cache location to be accessed, with one or more of the processor cores configured to transmit a message over the interconnection network to identify a synchronization operation to be performed with respect to the memory.
26. The apparatus of claim 25 , wherein the synchronization operation comprises reading stored data from an address in the memory and writing a data value included in the message into the memory address after the stored data is read, where reading the stored data and writing the data value occur atomically.