IP Library Granted Patent US 8,086,554
Granted Patent B1
US 8,086,554 · App. 13/188,580 · Granted Dec 27, 2011

Pattern matching in a multiprocessor environment

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Quick Facts
Patent No.
US 8,086,554
App. No.
13/188,580
Granted
Dec 27, 2011
Kind
B1
Abstract

Pattern matching in a plurality of interconnected processing engines includes: accepting a stream of input sequences over an interface and storing the input sequences; storing instructions for matching an input sequence to one or more patterns in memory accessible by a first set of one or more processing engines, and storing instructions for matching an input sequence to one or more patterns in memory accessible by a second set of one or more processing engines; distributing information identifying selected input sequences to the first and second sets of processing engines; and retrieving the identified input sequences to perform pattern matching in the first and second sets of processing engines.

Claims (23)

1. A method for pattern matching, including:

accepting at least one input sequence of symbols over an interface;

accepting a specification of state transitions among states associated with a finite state automaton for matching an input sequence to one or more patterns, wherein one or more of the states are associated with state transitions corresponding to a deterministic finite automaton and one or more states are associated with state transitions corresponding to a non-deterministic finite automaton, and with at least one state transition between a deterministic finite automaton state and a non-deterministic finite automaton state;

storing data that specifies the state transitions; and

determining whether the accepted input sequence matches the pattern based on the stored data.

2. The method of claim 1 , wherein at least some of the state transitions corresponding to a non-deterministic finite automaton fail to a state associated with state transitions corresponding to a deterministic finite automaton.

3. The method of claim 2 , wherein all of the state transitions corresponding to a non-deterministic finite automaton fail to a state associated with state transitions corresponding to a deterministic finite automaton.

4. The method of claim 1 , wherein all of the state transitions corresponding to a non-deterministic finite automaton fail to the same failure state.

5. The method of claim 4 , wherein the failure state comprises an initial state of the finite state automaton.

6. The method of claim 4 , wherein the failure state comprises a state to which the largest number of state transitions terminate.

7. The method of claim 4 , wherein the finite state automaton does not include any direct state transitions to children of the failure state from a state other than the failure state.

8. The method of claim 1 , wherein determining whether the accepted input sequence matches the pattern comprises, for a given symbol in the input sequence, accessing a first portion of the stored data that determines a state transition from a current state in parallel with accessing a second portion of the stored data that determines a state transition from a state to which the current state transitions if the given symbol fails to match a specified state transition from the current state.

9. The method of claim 8 , wherein accessing the first and second portions of the stored data in parallel comprises accessing the first and second portions in different execution units of a processing engine.

10. The method of claim 8 , wherein accessing the first and second portions of the stored data in parallel comprises accessing the first and second portions in different processing engines of an interconnected network of processing engines.

11. The method of claim 8 , wherein accessing the first and second portions of the stored data in parallel comprises overlapping execution of instructions associated with accessing the first and second portions in a pipeline.

12. A system for pattern matching, comprising:

a plurality of interconnected processing engines;

an interface to at least one of the processing engines configured to accept at least one input sequence of symbols; and

memory accessible by one or more of the processing engines that stores data that specifies state transitions among states associated with a finite state automaton for matching an input sequence to one or more patterns, wherein one or more of the states are associated with state transitions corresponding to a deterministic finite automaton and one or more states are associated with state transitions corresponding to a non-deterministic finite automaton;

at least one of the processing engines being configured to determine whether the accepted input sequence matches the pattern based on the stored data that specifies the state transitions, and with at least one state transition between a deterministic finite automaton state and a non-deterministic finite automaton state.

13. The system of claim 12 , wherein at least some of the state transitions corresponding to a non-deterministic finite automaton fail to a state associated with state transitions corresponding to a deterministic finite automaton.

14. The system of claim 13 , wherein all of the state transitions corresponding to a non-deterministic finite automaton fail to a state associated with state transitions corresponding to a deterministic finite automaton.

15. The system of claim 12 , wherein all of the state transitions corresponding to a non-deterministic finite automaton fail to the same failure state.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL AT REEL/FRAME NO. 42962/0859 Recorded Jul 13, 2018
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MELLANOX TECHNOLOGIES, LTD.; MELLANOX TECHNOLOGIES TLV LTD.; MELLANOX TECHNOLOGIES SILICON PHOTONICS INC.
Reel/Frame 046551/0459 →
SECURITY INTEREST Recorded Jun 23, 2017
From: MELLANOX TECHNOLOGIES, LTD.; MELLANOX TECHNOLOGIES TLV LTD.; MELLANOX TECHNOLOGIES SILICON PHOTONICS INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 042962/0859 →
DIVIDEND DECLARATION FROM EZCHIP SEMICONDUCTOR INC. TO THE STOCKHOLDER OF RECORD ON 6/2/2015 (EZCHIP INC., A DELAWARE CORPORATION) Recorded Feb 16, 2017
From: EZCHIP SEMICONDUCTOR INC.
To: EZCHIP, INC.
Reel/Frame 041736/0013 →
PURCHASE AGREEMENT Recorded Feb 16, 2017
From: EZCHIP, INC.
To: EZCHIP SEMICONDUCTOR LTD.
Reel/Frame 041736/0151 →
MERGER Recorded Feb 16, 2017
From: EZCHIP TECHNOLOGIES LTD.
To: EZCHIP SEMICONDUCTOR LTD.
Reel/Frame 041736/0321 →
MERGER Recorded Feb 16, 2017
From: EZCHIP SEMICONDUCTOR LTD.
To: MELLANOX TECHNOLOGIES, LTD.
Reel/Frame 041870/0455 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 16, 2017
From: EZCHIP SEMICONDUCTOR LTD.
To: EZCHIP TECHNOLOGIES, LTD.
Reel/Frame 041736/0253 →
MERGER Recorded Feb 16, 2017
From: TILERA CORPORATION
To: EZCHIP SEMICONDUCTOR INC.
Reel/Frame 041735/0792 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2011
From: STEELE, KENNETH M.; AGARWAL, ANANT
To: TILERA CORPORATION
Reel/Frame 026640/0470 →