High performance, scalable multi chip interconnect
A flexible, scalable server is described. The server includes plural server nodes each server node including processor cores and switching circuitry configured to couple the processor to a network among the cores with the plurality of cores implementing networking functions within the compute nodes wherein the plurality of cores networking capabilities allow the cores to connect to each other, and to offer a single interface to a network coupled to the server.
1. A server node, comprising:
a plurality of tiled compute nodes in a node stack topology, with multiple ones of the plurality of tiled compute nodes each comprising:
an array of interconnected tiles with each of the tiles including a processor and a switch with switches of the tiles configured to couple the array of interconnected tiles to network among the processors; and
switching circuitry configured to couple the plurality of tiled compute nodes to an external network, with the switching circuitry configured to provide network functions within the server node.
2. The server node of claim 1 wherein the networking switching functions within the server node are further configured to:
connect the plurality of tiled compute nodes to offer a single interface to the external network coupled to the server node.
3. The server node of claim 1 wherein each of the plurality of tiled compute nodes includes a layer 2 switch that uses media access control addresses for forwarding frames and with the plurality of tiled compute nodes arranged in the stacked node topology.
4. The server node of claim 3 wherein the layer 2 switch corresponds to the Open Systems Interconnection model and which uses media access control addresses for forwarding frames.
5. The server node of claim 1 wherein the server node is configured to execute an operating system and execute application programs under control of the operating system.
6. The server node of claim 1 wherein the server node is configured to add additional tiled compute nodes to the server node, and with the switching circuitry configured to couple the plurality of tiled compute nodes including the added additional tiled compute nodes to the external network.
7. The server node of claim 1 wherein each of the plurality of tiled compute nodes includes a layer 2 switch to couple the corresponding compute node to the external network, and the server node is configured with networking functions in the tiled compute nodes that are arranged in the stacked node topology to provide scalable node-stacking.
8. The server node of claim 6 wherein the scalable node stacking reduces the number of network ports required in the server node.
9. The server node of claim 1 wherein network functions are implemented with software or firmware that configure processors in the tiled compute nodes.
10. The server node of claim 1 wherein the server node is configured with fast path software that processes network processing tasks according to whether the processing task is a common task or an uncommon task.
11. The server node of claim 1 wherein the server node is configured with address-based routing.
12. A server node, comprising:
a plurality of tiled compute nodes in a node stack topology, with multiple ones of the plurality of tiled compute nodes each comprising:
an array of interconnected tiles with each of the tiles including a processor and a switch with switches of the tiles configured to couple the array of interconnected tiles to an internal network among the processors; and
switching circuitry including a layer 2 switch in each of the tiled compute nodes that is configured to couple the plurality of tiled compute nodes to an external network, with the switching circuitry configured to provide network functions within the server node by connecting the plurality of tiled compute nodes to the external network to offer a single interface to the external network coupled to the server node.
13. The server node of claim 12 wherein the layer 2 switch corresponds to the Open Systems Interconnection model and uses media access control addresses for forwarding frames.
14. The server node of claim 12 wherein the server node is configured to execute an operating system and execute application programs under control of the operating system.
15. The server node of claim 12 wherein the server node is configured to add additional tiled compute nodes to the server node, and with the switching circuitry configured to couple the plurality of tiled compute nodes including the added additional tiled compute nodes to the external network.
16. The server node of claim 12 wherein the stacked node topology reduces the number of network ports required in the server node and network functions are implemented with software or firmware that configure processors in the tiled compute nodes.
17. The server node of claim 1 wherein the server node is configured with fast path software that processes network processing tasks according to whether the processing task is a common task or an uncommon task.
18. The server node of claim 1 wherein the server node is configured with address-based routing.