IP Library Granted Patent US 8,392,661
Granted Patent B1
US 8,392,661 · App. 12/885,994 · Granted Mar 5, 2013

Managing cache coherence

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,392,661
App. No.
12/885,994
Granted
Mar 5, 2013
Kind
B1
Abstract

Managing data in a computing system comprising a plurality of cores includes assigning home cache locations of at least a first type of data associated with a first process executing on a first core to respective caches of one or more of the plurality of cores. Cores other than a home core, whose cache includes a home cache location for given cached data, access the given cached data by communicating with the home core. Home cache locations of at least a second type of data associated with the first process are assigned to a local cache of the first core. In response to migrating the first process to execute on a second core, home cache locations of the second type of data associated with the first process are re-assigned to a local cache of the second core.

Claims (24)

1. A method for managing data in a computing system comprising a plurality of cores, the method comprising:

assigning home cache locations of at least a first type of data associated with a first process executing on a first core to respective caches of one or more of the plurality of cores, with cores other than a home core, whose cache includes a home cache location for given cached data, accessing the given cached data by communicating with the home core;

assigning home cache locations of at least a second type of data associated with the first process to a local cache of the first core; and

in response to migrating the first process to execute on a second core, re-assigning home cache locations of the second type of data associated with the first process to a local cache of the second core.

2. The method of claim 1 , wherein the home cache locations of the first type of data associated with the first process are assigned to respective caches of multiple of the plurality of cores.

3. The method of claim 1 , wherein the first type of data associated with the first process comprises data that is included in an address space of the first process and is included in an address space of a second process.

4. The method of claim 3 , wherein the second type of data associated with the first process comprises data that is included in the address space of the first process and is not included in an address space of any other process.

5. The method of claim 3 , further comprising, after migrating the first process to execute on the second core, and in response to a request to swap a given portion of the first type of data associated with the first process, re-assigning home cache locations of the given portion of the first type of data associated with the first process to a local cache of the second core.

6. The method of claim 1 , wherein the second type of data associated with the first process comprises data that is stored in a stack or heap for the first process.

7. The method of claim 1 , further comprising migrating the first process to execute on the second core in response to determining that a quantity of data that is associated with the first process and assigned a home cache location of the local cache of the first core is below a predetermined threshold.

8. The method of claim 1 , further comprising, in response to determining that a quantity of data that is associated with a second process and assigned a home cache location of the local cache of the first core is above the predetermined threshold, rejecting a request to migrate the second process from executing on the first core.

9. The method of claim 1 , further comprising re-assigning home cache location of data associated with the first process to a local cache of the second core in response to user input.

10. A computer-readable storage medium storing a computer program for managing data in a computing system comprising a plurality of cores, the computer program including instructions for causing the computing system to:

assign home cache locations of at least a first type of data associated with a first process executing on a first core to respective caches of one or more of the plurality of cores, with cores other than a home core, whose cache includes a home cache location for given cached data, accessing the given cached data by communicating with the home core;

assign home cache locations of at least a second type of data associated with the first process to a local cache of the first core; and

in response to migrating the first process to execute on a second core, re-assign home cache locations of the second type of data associated with the first process to a local cache of the second core.

11. A computing system, comprising:

a plurality of cores;

a memory interface for coupling at least one core to a memory;

caches included in at least some of the cores for caching data from the memory; and

processors in the cores configured to:

assign home cache locations of at least a first type of data associated with a first process executing on a first core to respective caches of one or more of the plurality of cores, with cores other than a home core, whose cache includes a home cache location for given cached data, accessing the given cached data by communicating with the home core;

assign home cache locations of at least a second type of data associated with the first process to a local cache of the first core; and

in response to migrating the first process to execute on a second core, re-assign home cache locations of the second type of data associated with the first process to a local cache of the second core.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL AT REEL/FRAME NO. 42962/0859 Recorded Jul 13, 2018
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MELLANOX TECHNOLOGIES, LTD.; MELLANOX TECHNOLOGIES TLV LTD.; MELLANOX TECHNOLOGIES SILICON PHOTONICS INC.
Reel/Frame 046551/0459 →
SECURITY INTEREST Recorded Jun 23, 2017
From: MELLANOX TECHNOLOGIES, LTD.; MELLANOX TECHNOLOGIES TLV LTD.; MELLANOX TECHNOLOGIES SILICON PHOTONICS INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 042962/0859 →
DIVIDEND DECLARATION FROM EZCHIP SEMICONDUCTOR INC. TO THE STOCKHOLDER OF RECORD ON 6/2/2015 (EZCHIP INC., A DELAWARE CORPORATION) Recorded Feb 16, 2017
From: EZCHIP SEMICONDUCTOR INC.
To: EZCHIP, INC.
Reel/Frame 041736/0013 →
PURCHASE AGREEMENT Recorded Feb 16, 2017
From: EZCHIP, INC.
To: EZCHIP SEMICONDUCTOR LTD.
Reel/Frame 041736/0151 →
MERGER Recorded Feb 16, 2017
From: EZCHIP TECHNOLOGIES LTD.
To: EZCHIP SEMICONDUCTOR LTD.
Reel/Frame 041736/0321 →
MERGER Recorded Feb 16, 2017
From: EZCHIP SEMICONDUCTOR LTD.
To: MELLANOX TECHNOLOGIES, LTD.
Reel/Frame 041870/0455 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 16, 2017
From: EZCHIP SEMICONDUCTOR LTD.
To: EZCHIP TECHNOLOGIES, LTD.
Reel/Frame 041736/0253 →
MERGER Recorded Feb 16, 2017
From: TILERA CORPORATION
To: EZCHIP SEMICONDUCTOR INC.
Reel/Frame 041735/0792 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 27, 2010
From: METCALF, CHRISTOPHER D.
To: TILERA CORPORATION
Reel/Frame 025207/0504 →