Managing memory requests based on priority
View Patent ↗Managing access to an external memory in a computing system comprising one or more cores includes: receiving memory requests to access a memory at a memory controller coupled to at least one of the cores; assigning, by the memory controller, respective priorities to the memory requests, the priorities being based on priority configuration information; providing access, by the memory controller, to the memory based on the memory requests according to the assigned priorities. Messages are received at the memory controller to modify the priority configuration information.
1. A method for managing access to an external memory in a computing system comprising one or more cores, the method comprising:
receiving memory requests to access a memory at a memory controller coupled to at least one of the cores;
assigning, by the memory controller, respective priorities to the memory requests, the assigned priorities defining priority levels associated with requests having various defined attributes and the priorities based on priority configuration information, with the priority configuration information being stored in a register in the memory controller and accessible to the memory controller, with the priority information being configurable by execution of special memory access instructions issued by any of the cores of the computing system, and with the priority configuration information including a priority control list having plural entries, each entry specifying a “rule” in a rule field, with the rule being an expression of a set of attributes associated with memory request that is used to assign a predetermined priority level specified in a priority field of the given entry to such types of memory requests;
providing access, by the memory controller, to the memory based on the memory requests according to the assigned priorities; and
receiving messages at the memory controller to modify the priority configuration information.
2. The method of claim 1 , wherein the memory controller controls access to memory external to a core to which the memory controller is coupled.
3. The method of claim 1 , wherein the memory controller controls access to memory internal to a core to which the memory controller is coupled.
4. The method of claim 1 , wherein assigning respective priorities to the memory requests based on priority configuration information comprises:
matching at least one attribute of a particular memory request to at least one attribute identified by a particular portion of the priority configuration information; and
assigning a priority to the particular request based on a predetermined priority level identified by the particular portion of the priority configuration information.
5. The method of claim 4 , wherein the particular portion of the priority configuration information comprises one of multiple entries in a list, with one or more of the entries comprising: one or more attributes associated with memory requests, and a corresponding priority level assigned to a memory request that has the one or more attributes.
6. The method of claim 1 , wherein at least two of the memory controllers are coupled to at least one of the cores, and different respective sets of priority configuration information are stored in the at least two memory controllers.
7. The method of claim 6 , a memory request to access a memory that is received at a particular memory controller is assigned a priority based on priority configuration information stored in the particular memory controller.
8. The method of claim 1 , wherein a portion of the priority configuration information that identifies one or more attributes and a corresponding priority level includes an attribute that identifies a source of a particular memory request in the computing system.
9. The method of claim 8 , wherein the computing system comprises multiple cores and the identified source is identified as being one of multiple predetermined sources that include the multiple cores.
10. The method of claim 8 , wherein the identified source is identified as being one of multiple predetermined sources that include one or more cores and one or more devices coupled to at least one core.
11. The method of claim 8 , wherein the identified source is identified as being one of multiple types of processes including an operating system process and a user process.
12. The method of claim 8 , wherein the identified source is identified as being a core in a first set of one or more cores configured to operate with lower overhead than a second set of one or more cores.
13. The method of claim 1 , wherein the computing system comprises multiple cores and a portion of the priority configuration information that identifies one or more attributes and a corresponding priority level includes an attribute that identifies one of multiple networks among the cores over which a particular memory request is received at the memory controller.
14. The method of claim 13 , wherein the portion of the priority configuration information identifies ones of multiple routes over the identified network over which the particular memory request is received at the memory controller.
15. The method of claim 1 , wherein a portion of the priority configuration information that identifies one or more attributes and a corresponding priority level includes an attribute that identifies a type of a particular memory request.
16. The method of claim 15 , wherein the identified type is identified as being one of multiple types of memory operations including at least one type of memory operation from the group consisting of: a read operation, a write operation, and a compare-and-exchange operation.
17. The method of claim 15 , wherein the identified type identifies whether or not the particular memory request is a prefetch request.
18. The method of claim 15 , wherein the identified type identifies whether the particular memory request is associated with a data stream or an instruction stream.
19. The method of claim 15 , wherein the identified type identifies whether or not the particular memory request is cache miss request.
20. The method of claim 19 , wherein the identified type identifies a level of a multilevel cache.
21. The method of claim 1 , wherein providing access to the memory based on the memory requests according to the assigned priorities comprises:
accessing memory coupled to a particular memory controller for memory requests received at the particular memory controller that have been assigned a higher priority before accessing the memory coupled to the particular memory controller for memory requests received at the particular memory controller that have been assigned a lower priority.
22. The method of claim 21 , wherein access is provided according to the assigned priorities for multiple memory requests to access the same memory address.
23. The method of claim 21 , wherein the priority configuration information assigns requests to read the memory a higher priority than requests to write the memory.
24. The method of claim 21 , wherein the priority configuration information assigns requests to access open pages in the memory a higher priority than requests to access closed pages in the memory.
25. The method of claim 21 , wherein the priority configuration information assigns requests that originate from a core in a first set of one or more cores configured to operate with lower overhead than a second set of one or more cores a higher priority than requests that originate from a core in the second set.
26. The method of claim 1 , wherein receiving messages at the memory controller to modify the configuration information comprises:
receiving a message to modify the configuration information based on information identifying which of multiple cores are active or information identifying which of the multiple cores are inactive.
27. The method of claim 1 , further including modifying the configuration information during execution of processes on the one or more cores in response to the received messages.
28. A computing system, comprising:
one or more cores; and
a memory controller including a register, the memory controller coupled to at least one of the cores configured to:
receive memory requests to access a memory at the memory controller;
assign respective priorities to the memory requests, the assigned priorities defining priority levels associated with requests having various defined attributes and the priorities based on priority configuration information, with the priority configuration information being stored in the register and accessible to the memory controller, with the priority information being configurable by execution of special memory access instructions issued by any of the cores of the computing system and with the priority configuration information including a priority control list having plural entries, each entry specifying a “rule” in a rule field, with the rule being an expression of a set of attributes associated with memory request that is used to assign a predetermined priority level specified in a priority field of the given entry to such types of memory requests;
provide access to the memory based on the memory requests according to the assigned priorities; and
receive messages to modify the priority configuration information.
29. The computing system of claim 28 , wherein assigning respective priorities to the memory requests based on priority configuration information comprises:
matching at least one attribute of a particular memory request to at least one attribute identified by a particular portion of the priority configuration information; and
assigning a priority to the particular request based on a predetermined priority level identified by the particular portion of the priority configuration information.
30. The computing system of claim 29 , wherein the particular portion of the priority configuration information comprises one of multiple entries in a list, with one or more of the entries comprising: one or more attributes associated with memory requests, and a corresponding priority level assigned to a memory request that has the one or more attributes.
31. The computing system of claim 28 , wherein at least two of the memory controllers are coupled to at least one of the cores, and different respective sets of priority configuration information are stored in the at least two memory controllers.
32. The computing system of claim 31 , a memory request to access a memory that is received at a particular memory controller is assigned a priority based on priority configuration information stored in the particular memory controller.
33. The computing system of claim 31 , wherein a portion of the priority configuration information that identifies one or more attributes and a corresponding priority level includes an attribute that identifies a source of a particular memory request in the computing system, with the computing system comprising multiple cores and the identified source is identified as being one of multiple predetermined sources that include the multiple cores.
34. The computing system of claim 33 , wherein the identified source is identified as being one of multiple predetermined sources that include one or more cores and one or more devices coupled to at least one core.
35. The computing system of claim 34 , wherein the identified source is identified as being one of multiple types of processes including an operating system process and a user process.