IP Library Granted Patent US 10,210,092
Granted Patent B1
US 10,210,092 · App. 14/967,665 · Granted Feb 19, 2019

Managing cache access and streaming data

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Quick Facts
Patent No.
US 10,210,092
App. No.
14/967,665
Granted
Feb 19, 2019
Kind
B1
Abstract

Managing data in a computing system comprising one or more cores includes: providing a cache in each of one or more of the cores that includes multiple storage locations; storing data of a first type of multiple types of data in a selected storage location of a first cache of a first core that is selected according to status information associated with the first cache, and updating the status information; and storing data of a second type of the multiple types of data in a storage location within a subset of fewer than all of the storage locations of the first cache and managing the status information to ensure that subsequent data of the second type received by the first core for storage in the first cache is stored in the storage location within the subset.

Claims (50)

1. A method for managing first and second different types of data in a computing system comprising a multi-core processor comprising a plurality of cores with each core comprising a processor, a cache memory and a switch, the method comprising:

reading a status configuration register that is accessible to a processor of a core of a home cache, which status configuration register stores status information for the home cache;

storing data of a first type in a selected storage location of the home cache of a first core of the plurality of cores, with the selected storage location selected according to the status information for the home cache;

updating the status information in the status configuration register upon storage of the data of the first type, according to a least recently used update policy;

storing data of a second, different type in a second, different non-overlapping storage location of the home cache; and

managing the status information in the status register upon storage of the data of the second, different type to ensure that subsequent data of the second type received by the first core for storage in the home cache are stored in the second, different non-overlapping-storage location, without updating the least recently used status information for the second, different non-overlapping storage location.

2. The method of claim 1 , further including setting a configuration indicator that provides the status information in response to receiving the data of the second type.

3. The method of claim 2 , wherein data of the first type or the second, different type received while the configuration indicator is set is stored in a storage location within the second, different non-overlapping storage location.

4. The method of claim 1 , wherein the first type of data comprises data that is written or read by an instruction issued by a processor of at least one of the cores.

5. The method of claim 1 , wherein the second type of data comprises data that is received by at least one of the cores from an input/output device coupled to at least one of the cores.

6. The method of claim 5 , wherein the second type data comprises data that is streamed from the input/output device.

7. The method of claim 1 , wherein the home first cache is a set-associative cache having multiple sets to which different addresses are mapped and each set having multiple ways, the selected storage location includes a respective way in each set of the set-associative cache, the status information includes a least recently used (LRU) status that indicates which of the multiple ways in a given set stores data has been least recently used by a processor of at least one of the cores, and the selected storage location storing the data of the first type corresponds to the least recently used way of a set to which an address of the first type of data is mapped.

8. The method of claim 1 wherein managing the status information includes setting a configuration indicator stored in the configuration register in the first core to cause a least recently used (LRU) status to not be updated after storing data in the second, different non-overlapping storage location.

9. The method of claim 1 , wherein the selected and the second, different non-overlapping storage locations are two of multiple storage locations of the cache and which are respective ways of the cache that operates according to a set associative caching scheme; and

managing the status information includes setting a configuration indicator stored in the configuration register in the first core to cause a least recently used (LRU) status for a given set that corresponds to the second, different non-overlapping storage location to not be updated after storing data in the given set.

10. A computer-readable hardware storage device storing a computer program for managing data in a computing system comprising a multi-core processor comprising a plurality of cores with each core comprising a processor, a cache memory and a switch, the computer program including executable instructions for causing the computing system to:

read a status configuration register that is accessible to a processor of a core of a home cache, which status configuration register stores status information for the home cache;

store data of a first type of multiple types of data in a selected storage location of the home cache of a first core of the plurality of cores, with the selected storage location selected according to the status information for the home cache;

update the status information in the status configuration register upon storage of the data of the first type, according to a least recently used update policy;

store data of a second, different type of data in a second, different non-overlapping storage location of the home cache; and

manage the status information in the status register upon storage of the data of the second, different type to ensure that subsequent data of the second type received by the first core for storage in the home cache are stored in the second, different non-overlapping storage location, without updating the least recently used status information for the second, different non-overlapping storage location.

11. The computer-readable hardware storage device of claim 10 wherein the computer program further comprises instructions to:

set a configuration indicator that provides the status information in response to receiving the data of the second type.

12. The computer-readable hardware storage device of claim 11 wherein data of the first type or the second, different type received while the configuration indicator is set, is stored in a storage location within the second, different non-overlapping storage location.

13. The computer-readable hardware storage device of claim 10 wherein the first type of data comprises data that is written or read by an instruction issued by a processor of at least one of the cores.

14. The computer-readable hardware storage device of claim 10 wherein the second type of data comprises data that is received by at least one of the cores from an input/output device coupled to at least one of the cores.

15. The computer-readable hardware storage device storing a computer program of claim 14 , wherein the second type data comprises data that is streamed from the input/output device.

16. The computer-readable hardware storage device of claim 10 wherein the home cache is a set-associative cache having multiple sets to which different addresses are mapped and each set having multiple ways, the selected storage location includes a respective way in each set of the set-associative cache, the status information includes a least recently used (LRU) status that indicates which of the multiple ways in a given set stores data has been least recently used by a processor of at least one of the cores, and the selected storage location storing the data of the first type corresponds to the least recently used way of a set to which an address of the first type of data is mapped.

17. The computer-readable hardware storage device of claim 10 wherein the computer program further comprises instructions to:

manage the status information includes setting a configuration indicator stored in the configuration register in the first core to cause a least recently used (LRU) status to not be updated after storing data in the second, different non-overlapping storage location.

18. The computer-readable hardware storage device of claim 10 wherein the selected and the second, different non-overlapping storage locations are two of multiple storage locations of the cache and which are respective ways of the cache that operates according to a set associative caching scheme; and

managing the status information includes setting a configuration indicator stored in the configuration register in the first core to cause a least recently used (LRU) status for a given set that corresponds to the second, different non-overlapping storage location to not be updated after storing data in the given set.

19. A computing system, comprising:

one or more cores with each core comprising a processor and a cache;

a processor in a first core configured to:

read a status configuration register that is accessible to a processor of a core of a home cache, which status configuration register stores status information for the cache;

store data of a first type of multiple types of data in a selected storage location of a home cache of a first core, with the selected storage location selected according to the status information for the home cache;

update the status information in the status configuration register upon storage of the data of the first type, according to a least recently used update policy;

store data of a second, different type of the multiple types of data in a second, different non-overlapping storage location of the home cache; and

manage the status information in the status register upon storage of the data of the second, different type to ensure that subsequent data of the second type received by the first core for storage in the home cache are stored in the second, different non-overlapping storage location, without updating the least recently used status information for the second, different non-overlapping storage location.

20. The system of claim 19 , further configured to:

set a configuration indicator that provides the status information in response to receiving the data of the second type.

21. The system of claim 20 wherein data of the first type or the second, different type received while the configuration indicator is set is stored in a storage location within the second, different non-overlapping storage location.

22. The system of claim 19 wherein the first type of data comprises data that is written or read by an instruction issued by a processor of at least one of the cores.

23. The system of claim 22 , wherein the selected and the second, different non-overlapping storage locations are two of multiple storage locations of the cache and which are respective ways of the cache that operates according to a set associative caching scheme; and

managing the status information includes setting a configuration indicator stored in the configuration register in the first core to cause a least recently used (LRU) status for a given set that corresponds to the second, different non-overlapping storage location to not be updated after storing data in the given set.

24. The system of claim 19 wherein the second type of data comprises data that is received by at least one of the cores from an input/output device coupled to at least one of the cores.

25. The system of claim 24 wherein the second type data comprises data that is streamed from the input/output device.

26. The system of claim 19 wherein the home cache is a set-associative cache having multiple sets to which different addresses are mapped and each set having multiple ways, the selected storage location includes a respective way in each set of the set-associative cache, the status information includes a least recently used (LRU) status that indicates which of the multiple ways in a given set stores data has been least recently used by a processor of at least one of the cores, and the selected storage location storing the data of the first type corresponds to the least recently used way of a set to which an address of the first type of data is mapped.

27. The system of claim 19 wherein managing the status information includes setting a configuration indicator stored in the configuration register in the first core to cause a least recently used (LRU) status to not be updated after storing data in the second, different non-overlapping storage location.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 5, 2018
From: MIAO, CHYI-CHANG; METCALF, CHRISTOPHER D.; BRATT, IAN RUDOLF; RAMEY, CARL G.
To: TILERA CORPORATION
Reel/Frame 046788/0026 →
RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL AT REEL/FRAME NO. 42962/0859 Recorded Jul 13, 2018
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MELLANOX TECHNOLOGIES, LTD.; MELLANOX TECHNOLOGIES TLV LTD.; MELLANOX TECHNOLOGIES SILICON PHOTONICS INC.
Reel/Frame 046551/0459 →
SECURITY INTEREST Recorded Jun 23, 2017
From: MELLANOX TECHNOLOGIES, LTD.; MELLANOX TECHNOLOGIES TLV LTD.; MELLANOX TECHNOLOGIES SILICON PHOTONICS INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 042962/0859 →
DIVIDEND DECLARATION FROM EZCHIP SEMICONDUCTOR INC. TO THE STOCKHOLDER OF RECORD ON 6/2/2015 (EZCHIP INC., A DELAWARE CORPORATION) Recorded Feb 16, 2017
From: EZCHIP SEMICONDUCTOR INC.
To: EZCHIP, INC.
Reel/Frame 041736/0013 →
PURCHASE AGREEMENT Recorded Feb 16, 2017
From: EZCHIP, INC.
To: EZCHIP SEMICONDUCTOR LTD.
Reel/Frame 041736/0151 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 16, 2017
From: EZCHIP SEMICONDUCTOR LTD.
To: EZCHIP TECHNOLOGIES, LTD.
Reel/Frame 041736/0253 →
MERGER Recorded Feb 16, 2017
From: EZCHIP TECHNOLOGIES LTD.
To: EZCHIP SEMICONDUCTOR LTD.
Reel/Frame 041736/0321 →
MERGER Recorded Feb 16, 2017
From: EZCHIP SEMICONDUCTOR LTD.
To: MELLANOX TECHNOLOGIES, LTD.
Reel/Frame 041870/0455 →
MERGER Recorded Feb 16, 2017
From: TILERA CORPORATION
To: EZCHIP SEMICONDUCTOR INC.
Reel/Frame 041735/0792 →