Configuring routing in mesh networks
View Patent ↗A processor includes a plurality of processor tiles, each tile including a processor core, and an interconnection network interconnects the processor cores and enables transfer of data among the processor cores. The interconnection network has a plurality of dimensions in which an ordering of dimensions for routing data is configurable.
1. A processor, comprising:
a plurality of processor tiles, each tile comprising a processor core with processor cores of the tiles arranged in a two-dimensional array of rows and columns of processor cores, with a top row of processor cores connected to input/output ports that couple to corresponding input/output ports of a peripheral device; and
an interconnection network to interconnect the processor cores and enable transfer of data among the processor cores, the interconnection network having a plurality of dimensions in which an ordering of dimensions for routing data is configurable, with the interconnection network having a first dimension and a second dimension, and the interconnection network is selectable between at least two configurations, the first configuration routing data along the first dimension before routing the data along the second dimension, the second configuration routing data along the second dimension before routing the data along the first dimension, and when there are more data being sent from the peripheral device to the processor cores, the interconnection network is configured to route data along a column direction followed by routing the data along a row direction and when there are more data being sent from the processor cores to the peripheral device, the interconnection network is configured to route data along a row direction followed by routing the data along a column direction.
2. The processor of claim 1 , wherein the peripheral device comprises a memory controller interface.
3. The processor of claim 1 in which the ordering of dimensions for routing data is configurable by software.
4. The processor of claim 3 in which the software comprises an operating system or a hypervisor.
5. The processor of claim 1 , further comprising a register to store information indicating the ordering of dimensions for routing data.
6. The processor of claim 1 in which the mesh network has an X-dimension, a Y-dimension, and a Z-dimension, and the mesh network is selectable among six configurations that route data in the order of (X, Y, Z), (X, Z, Y), (Y, X, Z), (Y, Z, X), (Z, X, Y), and (Z, Y, X) dimensions, respectively.
7. The processor of claim 1 in which the mesh network has N dimensions, N being an integer, and the mesh network is selectable among N! configurations that route data along the N dimensions in various orderings.
8. The processor of claim 1 in which each tile comprises a routing arbiter to determine a path for routing data through the mesh network.
9. The processor of claim 8 in which the routing arbiter determines an ordering of dimensions of the routing based on coordinates of the routing arbiter, destination coordinates of the data, and a dimension ordering policy by the routing arbiter comparing the packet destination with the routing arbiter X and Y coordinates to route the packet based on the comparison and information from the first dimension register.
10. The processor of claim 9 in which the routing arbiter routes the data in a dimension along a dimension having a highest priority specified in the dimension ordering policy if the arbiter and the destination of the data do not have any coordinates in common.
11. The processor of claim 1 in which the interconnection network comprises a mesh network.
12. The processor of claim 1 in which the ordering of dimensions for routing data is configured to reduce or eliminate a skin effect and increase throughput of the interconnection network.
13. A system comprising:
a processor comprising
a plurality of processor tiles, each tile having a coordinate, each tile comprising
a processor core, and
a routing arbiter to determine a path for routing data through a multi-dimensional interconnection network that interconnects the processor cores and enables transfer of data among the processor cores;
a memory controller having input/output ports that are coupled to corresponding input/output ports associated with some of the processor cores; and
a first dimension register that is programmed to store information indicating the ordering of dimensions for routing data;
wherein when each of the routing arbiters receives a packet, the routing arbiter queries the first dimension register to determine a dimension ordering policy, and determines an ordering of dimensions for routing the packet based on coordinates of the routing arbiter, destination coordinates of the packet, and the dimension ordering policy by the routing arbiter comparing the packet destination with the routing arbiter X and Y coordinates to route the packet based on the comparison and information from the first dimension register.
14. A processor, comprising:
a plurality of processor tiles, each tile comprising a processor core with the plurality of processor cores comprising a two-dimensional array of rows and columns of processor cores, a first row of processor cores connected to input/output ports that couple to corresponding input/output ports of a peripheral device; and
an interconnection network to interconnect the processor cores and enable transfer of data among the processor cores, the interconnection network having a plurality of dimensions in which a first ordering of dimensions is used for routing data from an input/output device to the processor cores, and a second ordering of dimensions is used for routing data from the processor cores to the input/output device, the second ordering of dimensions being different from the first ordering of dimensions with the interconnection network comprising a mesh I/O extension network having network links between ports of the I/O device and the processor tiles, and when there are more data being sent from the peripheral device to the processor cores, the first ordering of dimensions specifies that data are to be routed along a column direction followed by routing the data along a row direction.
15. A processor, comprising:
a plurality of processor tiles, each tile comprising a processor core with the plurality of processor cores comprising a two-dimensional array of rows and columns of processor cores, a first row of processor cores connected to input/output ports that couple to corresponding input/output ports of a peripheral device; and
an interconnection network to interconnect the processor cores and enable transfer of data among the processor cores, the interconnection network having a plurality of dimensions in which a first ordering of dimensions is used for routing data from an input/output device to the processor cores, and a second ordering of dimensions is used for routing data from the processor cores to the input/output device, the second ordering of dimensions being different from the first ordering of dimensions with the interconnection network comprising a mesh I/O extension network having network links between ports of the I/O device and the processor tiles, and there are more data being sent from the processor cores to the peripheral device, and the second ordering of dimensions specifies that data are to be routed along a row direction followed by routing the data along a column direction.