Computing in parallel processing environments

1. A computing system, comprising:

a plurality of cores;

a memory interface to couple at least one core to a memory;

a first level cache memory;

a second level cache memory; and

a cache control unit to control the first level cache memory and the second level cache memory, the cache control unit included in at least one of the cores for caching data from the memory, the cache control unit configured to:

receive a request to access a block of the memory;

determine whether the requested block satisfies a predetermined condition;

store the requested block in the first level cache memory and not the second level cache memory in response to the condition being met; and

store the requested block in both the first level cache memory and the second level cache memory in response to the condition not being met.

2. The computing system of claim 1 , wherein the condition being met comprises: the request to access the block being an initial request, or a working set of blocks associated with the requested block fitting in the first level cache memory; and the condition not being met comprises: the request to access the block being a non-initial request, and a working set of blocks associated with the requested block not fitting in the first level cache memory.

3. The computing system of claim 1 , wherein multiple of the plurality of cores each include a respective cache control unit to control a corresponding cache memory.

4. A computing system, comprising:

a plurality of cores, with multiple ones of the plurality of cores each including a respective cache memory;

a memory interface to couple at least one core to a memory; and

a cache control unit in at least a first core to control the respective cache memory in the first core, for caching data from the memory, the cache control unit configured to:

process access requests that originate at the first core access a first portion of cached data that is assigned a home cache location in a second core;

maintain a first count of a number of access requests processed by the first core to access the first portion of cached data;

maintain a second count of a number of the access requests that result in a cache miss at the cache memory in the first core; and

re-assign a home cache location of the first portion of cached data from the second core to the first core in response to a predetermined condition on a function of the second count to the first count.

5. A method for configuring a computing system for executing instructions, the method comprising:

configuring a plurality of single-step engines, at least two single-step engines being associated with different respective protection levels, with a first single-step engine associated with a first protection level being configured to single-step instructions at the first protection level or lower and not at higher protection levels; and

in response to an instruction associated with the first single-step engine being prepared for execution, triggering a corresponding single-step interrupt.

6. A method for processing packets in a multicore computing system that includes a plurality of cores, the method comprising:

configuring a first set of one or more of the plurality of cores to execute a program associated with data being communicated to or from the computing system in packets;

configuring a second set of multiple of the plurality of cores to process packets, with different packets distributed to different cores in the second set for processing based on characteristics of the packets including at least one of source, destination, and protocol, and

redistributing packets for processing from a first core, selected based at least in part on a quantity of packets being processed by the first core, to a second core, at a time that is determined pseudo-randomly.

7. A computing system, comprising:

a plurality of cores, with multiple ones of the plurality of cores each including at least one power supply interface configured to receive a power supply voltage, with a first power supply voltage level enabling at least a first domain of the core when the first power supply voltage is applied to the power supply interface, and a second power supply voltage level disabling the first domain when the second power supply voltage is applied to the power supply interface; and

a plurality of signal isolation transistors, each coupled to a signal conductor path that crosses between domains of respective first and second cores, the signal isolation transistors configured to switch on, to ground the signal path, in response to the first domain being disabled by a corresponding power supply interface, and configured to switch off in response to the first domain being enabled by the corresponding power supply interface.

8. A computing system, comprising:

a plurality of cores;

a memory interface to couple at least one core to a memory; and

a cache control unit to control a cache memory, the cache control unit included in one of the cores for caching data from the memory, the cache control unit configured to:

receive a request to access data in a memory line of the memory from a requesting core;

hash the memory line to identify a cache line to store cached data from the memory line;

hash an identifier of the requesting core to generate a hash value;

set directory information associated with the identified cache line, the directory information corresponding to the generated hash value; and

send the cached data to the requesting core.

9. The computing system of claim 8 , wherein at least some of the plurality of cores each include a respective cache control unit to control a corresponding cache memory.