Supporting secondary atomic operations using primary atomic operations
View Patent ↗Performing atomic operations in a computing system includes: acquiring a lock by performing a primary atomic operation that is directly supported in circuitry of the computing system on a first memory address in a memory of the computing system; accessing a second memory address in the memory of the computing system after the lock has been acquired; completing a secondary atomic operation based on accessing the second memory address; and releasing the acquired lock after the secondary atomic operation has been completed.
1. A method for performing atomic operations in a computing system, the method comprising:
acquiring a lock by performing a primary atomic operation that is directly supported in circuitry of the computing system on a first memory address in a memory of the computing system;
accessing a second memory address in the memory of the computing system after the lock has been acquired;
completing a secondary atomic operation based on accessing the second memory address; and
releasing the acquired lock after the secondary atomic operation has been completed.
2. The method of claim 1 , wherein the first memory address is one of multiple addresses in a pool of addresses that provide locks that are acquired using the primary atomic operation.
3. The method of claim 2 , wherein the second memory address is hashed to select one of the multiple addresses in the pool of addresses as the first memory address.
4. The method of claim 2 , wherein at least some of the multiple addresses are in memory in respective caches of different respective cores of the computing system.
5. The method of claim 1 , wherein the primary atomic operation is a test-and-set operation.
6. The method of claim 1 , wherein the second memory address is in a memory of a first core of the computing system and interrupts to a processor of the first core are prevented between the time the lock is acquired and the time the acquired lock is released.
7. The method of claim 6 , wherein the interrupts prevented include page-fault interrupts.
8. A computer program product tangibly stored on a computer-readable storage device, the computer program product including a computer program for performing atomic operations in a computing system, the computer program including instructions for causing the computing system to:
acquire a lock by performing a primary atomic operation that is directly supported in circuitry of the computing system on a first memory address in a memory of the computing system;
access a second memory address in the memory of the computing system after the lock has been acquired;
complete a secondary atomic operation based on accessing the second memory address; and
release the acquired lock after the secondary atomic operation has been completed.
9. The computer program product of claim 8 , wherein the first memory address is one of multiple addresses in a pool of addresses that provide locks that are acquired using the primary atomic operation.
10. The computer program product of claim 9 , further comprising instructions to:
hash the second memory address to select one of the multiple addresses in the pool of addresses as the first memory address.
11. The computer program product of claim 9 , wherein at least some of the multiple addresses are in memory in respective caches of different respective cores of the computing system.
12. The computer program product of claim 8 , wherein the primary atomic operation is a test-and-set operation.
13. The computer program product of claim 8 , wherein the second memory address is in a memory of a first core of the computing system, the at least one processor further configured to:
prevent interrupts to a processor of the first core between the time the lock is acquired and the time the acquired lock is released.
14. The computing system of program product of claim 13 , wherein the interrupts prevented include page-fault interrupts.
15. A computing system, comprising:
a memory;
circuitry supporting a primary atomic operation associated with the memory; and
at least one processor configured to:
acquire a lock by performing the primary atomic operation on a first memory address in the memory;
accessing a second memory address in the memory after the lock has been acquired;
completing a secondary atomic operation based on accessing the second memory address; and
releasing the acquired lock after the secondary atomic operation has been completed.
16. The computing system of claim 15 , wherein the first memory address is one of multiple addresses in a pool of addresses that provide locks that are acquired using the primary atomic operation.
17. The computing system of claim 16 , the at least one processor further configured to:
hash the second memory address to select one of the multiple addresses in the pool of addresses as the first memory address.
18. The computing system of claim 16 , wherein at least some of the multiple addresses are in memory in respective caches of different respective cores of the computing system.
19. The computing system of claim 15 , wherein the primary atomic operation is a test-and-set operation.
20. The computing system of claim 15 , wherein the second memory address is in a memory of a first core of the computing system, the at least one processor further configured to:
prevent interrupts to a processor of the first core between the time the lock is acquired and the time the acquired lock is released.
21. The computing system of claim 20 , wherein the interrupts prevented include page-fault interrupts.