Protection in a parallel processing environment using access information associated with each switch to prevent data from being forwarded outside a plurality of tiles
View Patent ↗An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles. The tile is configured to control access to a resource of the tile based on access information associated with the resource.
1. An integrated circuit, comprising:
a plurality of tiles, each tile configured to control access to a resource of the tile based on access information associated with the resource, with each tile comprising
a processor, and
a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles; and
with at least one subset of tiles of the plurality of tiles configured to control access to tiles that are not part of the subset of tiles based on access information associated with each outbound link directly connecting a switch of the subset of tiles with a switch of the tiles that are not part of the subset of tiles so that data are prevented from being forwarded outside of the subset of tiles in response to an instruction which attempts to forward data outside of the subset of tiles.
2. The integrated circuit of claim 1 , wherein the access information comprises a stored protection level, and the tile is configured to allow access to the resource if a protection level associated with a requested access is greater than or equal to the stored protection level associated with the resource.
3. The integrated circuit of claim 2 , wherein the tile includes a register accessible to the processor for storing the protection level associated with the resource.
4. The integrated circuit of claim 3 , wherein the tile includes a register accessible to the processor for storing the protection level associated with the requested access.
5. The integrated circuit of claim 3 , wherein the tile is configured to control access to the register by a processor instruction based on a protection level associated with the processor instruction.
6. The integrated circuit of claim 3 , wherein the protection level comprises one of a predetermined number of levels.
7. The integrated circuit of claim 6 , wherein the predetermined number is between 2 and 16.
8. The integrated circuit of claim 7 , wherein the predetermined number is 4.
9. The integrated circuit of claim 1 , wherein different subsets of tiles are configured to run independent operating systems.
10. The integrated circuit of claim 1 , wherein each tile of the subset that is directly connected to at least one tile that is not part of the subset is configured to trigger an interrupt in response to an instruction attempting to forward data to the at least one tile that is not part of the subset.
11. The integrated circuit of claim 1 , wherein the resource comprises a portion of the switch.
12. The integrated circuit of claim 11 , wherein the portion of the switch comprises an output port connecting the tile to another tile over a data path.
13. The integrated circuit of claim 12 , wherein the access information comprises a stop signal from the connected tile.
14. The integrated circuit of claim 13 , wherein the switch determines whether a request to transmit data to the connected tile is allowed based on a credit count and the stop signal.
15. The integrated circuit of claim 13 , wherein at least some of the tiles are configured to assert stop signals for each directly connected tile during a context switch of the processor.
16. The integrated circuit of claim 11 , wherein the switching circuitry is configured to forward data based at least in part on information included in the data to be forwarded.
17. The integrated circuit of claim 16 , wherein the switches interconnected by the data paths comprise two-dimensional mesh network.
18. The integrated circuit of claim 17 , wherein the switches are configured to route data using dimension ordered routing.
19. The integrated circuit of claim 17 , wherein access information for a plurality of switches prevents access to output switch ports to tiles outside of a rectangular shaped group of tiles.
20. The integrated circuit of claim 11 , wherein the switch includes circuitry for multiple networks, and, for each network, the tile includes a register accessible to the processor for storing access information associated with the network.
21. The integrated circuit of claim 1 , wherein the resource comprises a portion of the processor.
22. The integrated circuit of claim 1 , wherein each tile further comprises a memory coupled to the processor.
23. The integrated circuit of claim 22 , wherein the resource comprises addresses within the memory.
24. The integrated circuit of claim 23 , wherein the tile includes a buffer associated with the memory to control access to addresses within the memory.
25. The integrated circuit of claim 1 , wherein multiple tiles that are not part of the subset of tiles but are directly connected to a respective tile of the subset of tiles are configured to prevent data from being forwarded to the respective tile.
26. The integrated circuit of claim 25 , wherein all tiles that are not part of the subset of tiles but are directly connected to a respective tile of the subset of tiles are configured to prevent data from being forwarded to the respective tile.
27. The integrated circuit of claim 25 , wherein at least one tile that is not part of the subset of tiles but is directly connected to a tile of the subset of tiles is configured to allow data to be forwarded to the tile.
28. A method for processing instructions in an integrated circuit, the integrated circuit comprising a plurality of tiles, each tile comprising a processor and a switch, the method comprising:
processing instructions in a processor of a tile;
forwarding data received over data paths from other tiles to the processor and to switches of other tiles, and forwarding data received from the processor to switches of other tiles;
controlling access to a resource of the tile based on access information associated with the resource; and
configuring at least one subset of tiles of the plurality of tiles to control access to tiles that are not part of the subset of tiles based on access information associated with each outbound link directly connecting a switch of the subset of tiles with a switch of the tiles that are not part of the subset of tiles so that data are prevented from being forwarded outside of the subset of tiles in response to an instruction which attempts to forward data outside of the subset of tiles.