Hardware device safe mode
A startup sequence in a computer system is initiated by detecting a bus reset event in an I/O device connected to a host, and responsively to the bus reset event communicating resources required to be allocated by the host. When a startup command from a host driver is not received within a predetermined bus reset count, the device autonomously changes its current configuration to a safe mode configuration, wherein fewer resources are required to be allocated relative to the current configuration. The safe mode configuration is communicated from the device to the host.
1. A method of communication, comprising the steps of:
initiating a startup sequence in a computer system comprising a host and a device connected to the host by a bus, the host having a driver for the device;
detecting in the device a bus reset event from the host via the bus;
responsively to the bus reset event communicating a current configuration of the device to the host, the current configuration comprising resources required to be allocated by the host;
failing to receive via the bus a startup command from the driver within a predetermined bus reset count, wherein the predetermined bus reset count specifies a number of bus reset events that do not result in a successful initialization;
thereafter in the device autonomously modifying the current configuration to a safe mode configuration, wherein fewer resources are required to be allocated relative to the current configuration; and
communicating the safe mode configuration via the bus from the device to the host.
2. The method according to claim 1 , further comprising dispatching a notification of safe mode operation from the device to the driver and to an operating system in the host.
3. The method according to claim 1 , wherein the computer system is linked to a host manager server, further comprising the steps of:
communicating from the host manager server a safe mode instruction to the computer system, wherein the safe mode instruction specifies the number of bus reset events prior to entry into a safe mode of operation.
4. The method according to claim 1 , wherein modifying the current configuration is performed by a baseboard management controller in the host, the baseboard management controller being connected to the device via a side channel interface.
5. The method according to claim 1 , wherein the bus is a PCIe bus.
6. An I/O device, comprising:
a network interface linked to a data network;
a host interface connectable to a host computer by a bus and receiving instructions from a driver in the host computer;
processing circuitry comprising a bus monitor linked to the host interface, the processing circuitry configured for:
initiating a startup sequence responsively to a startup command from the driver;
detecting with the bus monitor a bus reset event from the host computer via the bus;
responsively to the bus reset event communicating a current configuration to the host computer, the current configuration comprising resources required to be allocated by the host computer;
failing to receive the startup command from the driver within a predetermined bus reset count, wherein the predetermined bus reset count specifies a number of bus reset events that do not result in a successful initialization;
thereafter autonomously modifying the current configuration to a safe mode configuration, wherein fewer resources are required to be allocated relative to the current configuration;
communicating the safe mode configuration via the bus to the host computer; and
exchanging data via the network interface in the safe mode configuration.
7. The device according to claim 6 , wherein the processing circuitry is configured for dispatching a notification of safe mode operation to the host computer.
8. The device according to claim 6 , wherein the host computer is linked to a host manager server, wherein the processing circuitry is configured for receiving a safe mode instruction that originates from the host manager server, the safe mode instruction specifying the number of bus reset events prior to entry into a safe mode of operation.
9. The device according to claim 6 , further comprising a side channel interface wherein the processing circuitry is configured for accepting a modification of the current configuration from a baseboard management controller in the host computer, the baseboard management controller being connected to the side channel interface.
10. The device according to claim 6 , wherein the bus is a PCIe bus.
11. A system, comprising:
a host computer having a driver;
a network device having a network interface linked to a data network, a host interface connected to the host computer by a bus and receiving instructions from the driver in the host computer and processing circuitry comprising a bus monitor linked to the host interface, the processing circuitry configured for:
initiating a startup sequence responsively to a startup command from the driver;
detecting with the bus monitor a bus reset event from the host computer via the bus;
responsively to the bus reset event communicating a current configuration to the host computer, the current configuration comprising resources required to be allocated by the host computer;
failing to receive the startup command from the driver within a predetermined bus reset count, wherein the predetermined bus reset count specifies a number of bus reset events that do not result in a successful initialization;
thereafter autonomously modifying the current configuration to a safe mode configuration, wherein fewer resources are required to be allocated relative to the current configuration;
communicating the safe mode configuration via the bus to the host computer; and
exchanging data via the network interface in the safe mode configuration.
12. The system according to claim 11 , wherein the processing circuitry is configured for dispatching a notification of safe mode operation to the host computer.
13. The system according to claim 11 , wherein the host computer is linked to a host manager server, wherein the processing circuitry is configured for receiving a safe mode instruction that originates from the host manager server, the safe mode instruction specifying the number of bus reset events prior to entry into a safe mode of operation.
14. The system according to claim 11 , wherein the network device further comprises a side channel interface and the processing circuitry is configured for accepting a modification of the current configuration from a baseboard management controller in the host computer, the baseboard management controller being connected to the side channel interface.
15. The system according to claim 11 , wherein the bus is a PCIe bus.