Memory system including a memory chip configured to receive an erase suspend command and a program suspend command from a controller chip
A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.
1. A memory system comprising:
a controller chip; and
a memory chip configured to receive a plurality of commands from the controller chip, the memory chip including a ready/busy pin, wherein
the memory chip is configured to output a first signal having a first busy state from the ready/busy pin after the memory chip receives an erase command, a first address, and an erase execute command in order,
while the memory chip outputs the first signal having the first busy state, the memory chip is configured to receive a suspend command,
after the memory chip receives the suspend command, the memory chip is configured to output the first signal having a first ready state from the ready/busy pin,
while the memory chip outputs the first signal having the first ready state, the memory chip is configured to receive a resume command,
after the memory chip receives the resume command, the memory chip is configured to output the first signal having a second busy state from the ready/busy pin.
2. The memory system according to claim 1 , wherein
the memory chip including a plurality of memory cells, the memory cells including a first memory cell and a second memory cell, the first memory cell being provided above a semiconductor substrate, the second memory cell being provided above the first memory cell.
3. The memory system according to claim 1 , wherein
the memory chip includes a first I/O pin and a second I/O pin, the memory chip is configured to output a second signal through the first I/O pin and output a third signal through the second I/O pin after the memory chip receives a status command, the second signal indicating whether a program operation is completed or not, the third signal indicating whether a result of the program operation is pass or not.
4. The memory system according to claim 3 , wherein
the memory chip further includes a status register which can store the second signal and the third signal.
5. The memory system according to claim 3 , wherein
the memory chip including a plurality of memory cells, the memory cells including a first memory cell and a second memory cell, the first memory cell being provided above a semiconductor substrate, the second memory cell being provided above the first memory cell.
6. The memory system according to claim 1 , wherein while the memory chip outputs the first signal having the first busy state, the memory chip performs an erase operation and a program operation.
7. The memory system according to claim 6 , wherein after the memory chip receives the suspend command, the memory chip suspends the program operation, and after the memory chip receives the resume command, the memory chip resumes the program operation.
8. The memory system according to claim 6 , wherein
the memory chip includes a first I/O pin and a second I/O pin, the memory chip is configured to output a second signal through the first I/O pin and output a third signal through the second I/O pin after the memory chip receives a status command, the second signal indicating whether the program operation is completed or not, the third signal indicating whether a result of the program operation is pass or not.
9. The memory system according to claim 1 , wherein while the memory chip outputs the first signal having the first ready state, the memory chip is configured to receive a read address input command, a second address, and a read execute command in order, and
after the memory chip receives the read execute command, the memory chip outputs the first signal having a third busy state from the ready/busy pin.
10. The memory system according to claim 9 , wherein the memory chip performs a read operation after the memory chip receives the read execute command, and after the read operation is completed, the memory chip is configured to output the first signal having a second ready state from the ready/busy pin, and
while the memory chip outputs the first signal having the second ready state, the memory chip is configured to receive a second resume command,
after the memory chip receives the second resume command, the memory chip is configured to output the first signal having a fourth busy state from the ready/busy pin.