IP Library Granted Patent US 10,134,908
Granted Patent B2
US 10,134,908 · App. 15/363,386 · Granted Nov 20, 2018

Semiconductor device and manufacturing method thereof

Inventors: Tatsuo Nakayama (Ibaraki, JP); Hironobu Miyamoto (Ibaraki, JP); Yasuhiro Okamoto (Ibaraki, JP)
Assignee: Renesas Electronics Corporation
H01L29/78681H01L21/3006H01L29/2003H01L29/66522
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Quick Facts
Patent No.
US 10,134,908
App. No.
15/363,386
Granted
Nov 20, 2018
Kind
B2
Abstract

A MISFET is formed to include: a co-doped layer that is formed over a substrate and has an n-type semiconductor region and a p-type semiconductor region; and a gate electrode formed over the co-doped layer via a gate insulation film. The co-doped layer contains a larger amount of Mg, a p-type impurity, than that of Si, an n-type impurity. Accordingly, the carriers (electrons) resulting from the n-type impurities (herein, Si) in the co-doped layer are canceled by the carriers (holes) resulting from p-type impurities (herein, Mg), thereby allowing the co-doped layer to serve as the p-type semiconductor region. Mg can be inactivated by introducing hydrogen into, of the co-doped layer, a region where the n-type semiconductor region is to be formed, thereby allowing the region to serve as the n-type semiconductor region. By thus introducing hydrogen into the co-doped layer, the p-type semiconductor region and the n-type semiconductor region can be formed in the same layer.

Claims (17)

1. A manufacturing method of a semiconductor device, comprising the steps of:

(a) forming, over a substrate, a nitride semiconductor layer containing p-type impurities and n-type impurities; and

(b) introducing hydrogen into a first region of the nitride semiconductor layer,

wherein the first region is allowed to serve as an n-type semiconductor region by the step (b),

wherein in the nitride semiconductor layer, a concentration of the p-type impurities is higher than a concentration of the n-type impurities.

2. The manufacturing method of a semiconductor device according to claim 1 ,

wherein the step (b) is a step in which hydrogen is diffused from a film, which is formed over the first region and contains hydrogen, into the first region by performing a heat treatment.

3. The manufacturing method of a semiconductor device according to claim 1 ,

wherein the step (b) includes the steps of:

(b1) ion implanting hydrogen by using a film having an opening in the first region as a mask; and

(b2) after the step (b1), performing a heat treatment.

4. The manufacturing method of a semiconductor device according to claim 1 ,

wherein in the step (b), hydrogen is not introduced into a second region of the nitride semiconductor layer, and the second region is a p-type semiconductor region.

5. The manufacturing method of a semiconductor device according to claim 1 , comprising the step of:

(c) forming a gate electrode over the nitride semiconductor layer via a gate insulation film.

6. The manufacturing method of a semiconductor device according to claim 1 ,

wherein the p-type impurity is Mg and the n-type impurity is Si.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 29, 2016
From: NAKAYAMA, TATSUO; MIYAMOTO, HIRONOBU; OKAMOTO, YASUHIRO
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 040454/0271 →
Priority Claims (1)
JP 2015-253628 · Dec 25, 2015 · national
Continuity (1)
Related Publication 20170186880A1 · Jun 29, 2017