Efficient signaling scheme for high-speed ultra short reach interfaces
View Patent ↗A master integrated circuit (IC) chip includes transmit circuitry and receiver circuitry. The transmit circuitry includes a timing signal generation circuit to generate a first timing signal, and a driver to transmit first data in response to the first timing signal. A timing signal path routes the first timing signal in a source synchronous manner with the first data. The receiver circuitry includes a receiver to receive second data from a slave IC chip, and sampling circuitry to sample the second data in response to a second timing signal that is derived from the first timing signal.
1. A master integrated circuit (IC) chip, comprising:
transmit circuitry including
a timing signal generation circuit to generate a first timing signal,
a data pin for coupling to a data path,
a driver to transmit first data via the data pin in response to the first timing signal, and
a timing signal pin separate from the data signal pin, the timing signal pin for coupling to a timing signal path separate from the data path, the timing signal path to route the first timing signal in a source synchronous manner with the first data; and
receiver circuitry including
a receiver to receive second data from a slave IC chip, and
sampling circuitry to sample the second data in response to a second timing signal that is derived from the first timing signal.
2. The master IC chip according to claim 1 , further comprising:
a phase alignment circuit to adjust a phase of the first timing signal to generate the second timing signal.
3. The master IC chip according to claim 2 , wherein:
the phase alignment circuit comprises a clock vernier.
4. The master IC chip according to claim 3 , wherein:
the second data is received at a symbol rate that is greater than 10GBaud.
5. The master IC chip according to claim 1 , wherein:
the second timing signal is derived from the first timing signal and received from the slave IC chip.
6. The master IC chip according to claim 5 , wherein:
the first timing signal and the second timing signal are transmitted between the master IC chip and the slave IC chip via a bidirectional link.
7. The master IC chip according to claim 1 , wherein:
the master IC chip comprises a serializer-deserializer (SerDes) core IC chip, and the slave IC chip comprises a network switch IC chip.
8. The master IC chip according to claim 1 , wherein:
the timing signal generator comprises a clock generator to generate a double-data-rate (DDR) clock.
9. A multi-chip module (MCM), comprising:
a chip substrate;
a master integrated circuit (IC) chip mounted to the chip substrate, the master IC chip comprising
transmit circuitry including
a timing signal generation circuit to generate a first timing signal,
a data pin for coupling to a data path,
a driver to transmit first data via the data pin in response to the first timing signal, and
a timing signal path separate from the data path to route the first timing signal in a source synchronous manner with the first data; and
a slave IC chip mounted to the chip substrate and coupled to the master IC chip via a data link, the slave IC chip including
a receiver to receive the first data from the master IC chip, and to sample the first data in response to the first timing signal, and
a transmitter to transmit second data to the master IC chip; and
wherein the master IC chip further comprises
receiver circuitry to receive the second data from the slave IC chip, and
sampling circuitry to sample the second data in response to a second timing signal that is derived from the first timing signal.
10. The master IC chip according to claim 9 , wherein the master IC chip further comprises:
a phase alignment circuit to adjust a phase of the first timing signal to generate the second timing signal.
11. The master IC chip according to claim 10 , wherein:
the phase alignment circuit comprises a clock vernier.
12. The master IC chip according to claim 11 , wherein:
the second data is received at a symbol rate that is greater than 10GBaud.
13. The master IC chip according to claim 9 , wherein:
the second timing signal is derived from the first timing signal and received from the slave IC chip.
14. The master IC chip according to claim 13 , wherein:
the first timing signal and the second timing signal are transmitted between the master IC chip and the slave IC chip via a bidirectional link.
15. The master IC chip according to claim 9 , wherein:
the master IC chip comprises a serializer-deserializer (SerDes) core IC chip, and the slave IC chip comprises a network switch IC chip.
16. The master IC chip according to claim 9 , wherein:
the timing signal generator comprises a clock generator to generate a double-data-rate (DDR) clock.
17. A method of operation in a master integrated circuit (IC) chip, the method comprising:
generating a first timing signal;
transmitting first data via a data pin in response to the first timing signal, and
transmitting the first timing signal via a timing signal pin in a source synchronous manner with the first data to a slave IC chip, the timing signal pin separate from the data pin;
receiving second data from the slave IC chip; and
sampling the second data in response to a second timing signal that is derived from the first timing signal.
18. The method according to claim 17 , further comprising:
receiving the second timing signal from the slave IC chip.
19. The method according to claim 17 , further comprising:
phase aligning the first timing signal to generate the second timing signal.
20. The method according to claim 19 , wherein:
the phase aligning is carried out in the master IC chip.