ESD protection device

1. An electrostatic discharge (ESD) protection device comprising:

a resistor-capacitor (RC) trigger circuit;

a driver circuit comprising two parallel branches, they are both configured to receive an ESD protection signal from the RC trigger circuit; and

a discharge circuit comprising a first metal oxide semiconductor (MOS) transistor and a second MOS transistor connected in series between a first voltage potential and a second voltage potential, the driver circuit providing one or more signals for turning the first and second MOS transistors on and off;

wherein when an ESD spike is applied to the first voltage potential, the ESD protection signal from the RC trigger circuit turns on both the first and second MOS transistors.

2. The ESD protection device of claim 1 , wherein the first MOS transistor has a gate terminal electrically connected to a first node of the driver circuit, and the second MOS transistor has a gate terminal electrically connected to a second node of the driver circuit.

3. The ESD protection device of claim 1 , wherein when the first and second transistors are turned off, (i) a gate terminal of the first MOS transistor is shorted to a source terminal of the first MOS transistor via a first circuit path, and (ii) a gate terminal of the second MOS transistor is shorted to a source terminal of the second MOS transistor via a second circuit path that is different than the first circuit path.

4. The ESD protection device of claim 1 , wherein the driver circuit comprises:

a third MOS transistor having first and second source/drain terminals, the first source/drain terminal coupled to a gate terminal of the first MOS transistor, and the second source/drain terminal coupled to a source terminal of the first MOS transistor; and

a fourth MOS transistor having third and fourth source/drain terminals, the third source/drain terminal coupled to a gate terminal of the second MOS transistor, and the fourth source/drain terminal coupled to a source terminal of the second MOS transistor.

5. The ESD protection device of claim 1 , wherein the RC trigger circuit, the driver circuit, and the discharge circuit are configured such that (i) a current flows through the first and second MOS transistors of the discharge circuit when an ESD spike is applied to the first voltage potential, and (ii) the first and second MOS transistors are turned off when the first voltage potential is free of ESD spikes.

6. The ESD protection device of claim 1 , wherein the RC trigger circuit includes a resistance element and a capacitance element coupled together at a node, and the driver circuit comprises (i) a first inverter having an input coupled to the node and an output coupled to a gate terminal of the first MOS transistor, and (ii) a second inverter having an input coupled to the node and an output coupled to a gate terminal of the second MOS transistor.

7. The ESD protection device of claim 6 , wherein

the first inverter comprises a first p-type MOS (PMOS) transistor and a first n-type MOS (NMOS) transistor connected in series between the first voltage potential and the second voltage potential, and

the second inverter comprises a second PMOS transistor and a second NMOS transistor connected in series between the first voltage potential and the second voltage potential.

8. The ESD protection device of claim 1 , wherein the first MOS transistor comprises a first NMOS transistor, and the second MOS transistor comprises a second NMOS transistor.

9. The ESD protection device of claim 1 , wherein the RC trigger circuit, the driver circuit, and the discharge circuit each has (i) a first terminal coupled to the first voltage potential, and a second terminal coupled to the second voltage potential.

10. The ESD protection device of claim 1 , wherein the first voltage potential is a positive supply voltage, and the second voltage potential is a ground voltage.

11. A discharge circuit of an electrostatic discharge (ESD) protection device, the discharge circuit comprising:

a first metal oxide semiconductor (MOS) transistor; and

a second MOS transistor connected in series with the first MOS transistor between a first voltage potential and a second voltage potential, the first and second MOS transistors being configured to receive one or more signals from a driver circuit for turning the first and second MOS transistors on and off, wherein when the first and second transistors are turned off, (i) a gate terminal of the first MOS transistor is shorted to a source terminal of the first MOS transistor via a first circuit path through a third MOS of the driver circuit, and (ii) a gate terminal of the second MOS transistor is shorted to a source terminal of the second MOS transistor via a second circuit path through a fourth MOS of the driver circuit;

wherein the second circuit path is different than the first circuit path; and

wherein gate terminals of the third MOS and the fourth MOS are directly coupled together.

12. The discharge circuit of claim 11 , wherein

the gate terminal of the first MOS transistor is electrically connected to a first node of the driver circuit, and

the gate terminal of the second MOS transistor is electrically connected to a second node of the driver circuit.

13. The discharge circuit of claim 11 , wherein the first MOS transistor comprises a first NMOS transistor, and the second MOS transistor comprises a second NMOS transistor.

14. The discharge circuit of claim 11 , wherein an ESD current flows through the first and second MOS transistors when an ESD spike is applied to the first voltage potential, and wherein the first and second MOS transistors are turned off when the first voltage potential is free of ESD spikes.

15. A method for protecting a device from an electrostatic discharge (ESD) event, the method comprising:

turning off a first metal oxide semiconductor (MOS) transistor and a second MOS transistor of a discharge circuit in an ESD protection device when a first voltage potential is free of ESD spikes;

wherein the ESD protection device comprises:

the discharge circuit,

a resistor-capacitor (RC) trigger circuit, and

a driver circuit comprising two parallel branches that are both configured to receive a same ESD protection signal from the RC trigger circuit; and

wherein the discharge circuit comprises the first and second MOS transistors being connected in series between the first voltage potential and a second voltage potential; and

when an ESD spike is applied to the first voltage potential, the RC trigger circuit generates an ESD protection signal; the ESD protection signal is received by the driver circuit comprising two parallel branches, which respectively turn on the first and second MOS transistors to cause an ESD current to flow through the transistors.

16. The method of claim 15 , wherein the turning off of the first and second MOS transistors comprises:

shorting a gate terminal of the first MOS transistor to a source terminal of the first MOS transistor; and

shorting a gate terminal of the second MOS transistor to a source terminal of the second MOS transistor.

17. The method of claim 16 , wherein the gate terminal of the first MOS transistor is shorted to the source terminal of the first MOS transistor via a first circuit path, and wherein the gate terminal of the second MOS transistor is shorted to the source terminal of the second MOS transistor via a second circuit path that is different than the first circuit path.

18. The discharge circuit of claim 11 , wherein the first voltage potential is a positive supply voltage, and the second voltage potential is a ground voltage.

19. The discharge circuit of claim 11 , wherein the driver circuit comprises:

the third MOS transistor having first and second source/drain terminals, the first source/drain terminal coupled to a gate terminal of the first MOS transistor, and the second source/drain terminal coupled to a source terminal of the first MOS transistor; and

the fourth MOS transistor having third and fourth source/drain terminals, the third source/drain terminal coupled to a gate terminal of the second MOS transistor, and the fourth source/drain terminal coupled to a source terminal of the second MOS transistor.

20. The method of claim 15 , wherein the first voltage potential is a positive supply voltage, and the second voltage potential is a ground voltage.