Method for eliminating false paths of a circuit unit to be implemented using a system

1. A system comprising:

a net-identifying module comprising an input receiver, an identifier, and an output provider, the net-identifying module configured to receive first and second electronic lists associated with a circuit unit, to identify a net of the circuit unit based on the first electronic list, and to provide a net information output that includes information associated with the net; and

a false path-eliminating module coupled to the net-identifying module and configured to eliminate a false path of the circuit unit in the second electronic list based on the net information output,

wherein the net-identifying module is further configured to count the number of source/drain terminals of the circuit unit coupled to a THROUGH node of the circuit unit.

2. The system of claim 1 , wherein the net-identifying module is further configured to replace parallel transistors of the circuit unit with a single transistor.

3. The system of claim 2 , wherein the net-identifying module is further configured to compare the numbers of source/drain terminals of the circuit unit connected to a THROUGH node of the circuit unit prior to and after replacing the parallel transistors with the single transistor.

4. The system of claim 3 , wherein the net-identifying module is further configured to identify a component of the circuit unit coupled to the THROUGH node as the net based on the result of comparison.

5. The system of claim 1 , wherein the net-identifying module is further configured to determine whether the circuit unit includes a FROM node that has different numbers of p-type and n-type transistors of the circuit unit coupled thereto.

6. The system of claim 1 , wherein the false path-eliminating module is further configured to select in the second electronic list a path of the circuit unit that does not traverse through the net and to provide a path information output that includes information associated with the path.

7. The system of claim 1 , wherein the false path-eliminating module is further configured to select in the second electronic list a path of the circuit unit that traverses through the net and to remove the path from the second electronic list.

8. The system of claim 1 , wherein the false path-eliminating module is further configured to enable circuit analysis of the circuit unit having the false path eliminated.

9. A method comprising:

receiving first and second electronic lists associated with a circuit unit, the circuit unit comprising an input receiver, an identifier, and an output provider, the net-identifying module;

identifying a net of the circuit unit based on the first electronic list;

providing a net information output that includes information associated with the net;

selecting in the second electronic list a path of the circuit unit that traverses through the net;

removing the path from the second electronic list; and

counting the number of source/drain terminals of the circuit unit coupled to a THROUGH node of the circuit unit.

10. The method of claim 9 , further comprising replacing parallel transistors of the circuit unit with a single transistor.

11. The method of claim 10 , further comprising comparing the numbers of source/drain terminals of the circuit unit coupled to a THROUGH node of the circuit unit prior to and after replacing the parallel transistors with the single transistor.

12. The method of claim 11 , further comprising identifying a component of the circuit unit coupled to the THROUGH node as the net based on the result of comparison.

13. The method of claim 9 , further comprising determining whether the circuit unit includes a FROM node that has different numbers of p-type and n-type transistors of the circuit unit coupled thereto.

14. The method of claim 9 , further comprising performing analysis of the circuit unit having the false path eliminated.

15. A controller having computer-readable program instructions, which when executed result in operations comprising:

accessing a plurality of lists associated with a circuit unit from a computer-readable memory;

extracting a net of the circuit unit based on at least one list of the plurality of lists;

generating a net information output that includes information associated with the net;

identifying, in another list of the plurality of lists, a path of the circuit unit that traverses through the net; and

removing the path from the another list,

wherein the operations further comprise determining the number of source/drain terminals of the circuit unit coupled to a THROUGH node of the circuit unit.

16. The controller of claim 15 , wherein the operations further comprise substituting parallel transistors of the circuit unit with a single transistor.

17. The controller of claim 16 , wherein the operations further comprise comparing the numbers of source/drain terminals of the circuit unit coupled to a THROUGH node of the circuit unit prior to and after substituting the parallel transistors with the single transistor.

18. The controller of claim 17 , wherein the operations further comprise determining a component of the circuit unit coupled to the THROUGH node as the net based on the result of comparison.

19. The controller of claim 15 , wherein the operations further comprise identifying whether the circuit unit includes a FROM node that has different numbers of transistor types of the circuit unit coupled thereto.

20. The controller of claim 15 , wherein the operations further comprise performing analysis of the circuit unit having the false path eliminated.