FinFETs having epitaxial capping layer on fin and methods for forming the same
A FinFET and methods for forming a FinFET are disclosed. A method includes forming a semiconductor fin on a substrate, implanting the semiconductor fin with dopants, and forming a capping layer on a top surface and sidewalls of the semiconductor fin. The method further includes forming a dielectric on the capping layer, and forming a gate electrode on the dielectric.
1. A method comprising:
patterning a semiconductor substrate to form a semiconductor fin on the semiconductor substrate, the patterning forming a top surface and sidewalls of the semiconductor fin, the top surface and the sidewalls of the semiconductor fin having a same material composition;
forming an isolation region on the semiconductor substrate, the isolation region surrounding the semiconductor fin;
implanting dopants into the semiconductor fin;
after implanting dopants into the semiconductor fin, recessing the isolation region to expose an upper portion of the semiconductor fin;
homoepitaxially growing a capping layer from the top surface and sidewalls of the semiconductor fin, the top surface and the sidewalls of the semiconductor fin being on the upper portion of the semiconductor fin; and
forming a gate dielectric layer over the capping layer, the gate dielectric layer contacting sidewalls of the capping layer and the semiconductor fin.
2. The method of claim 1 , wherein the capping layer has a thickness from 2 nm to 6 nm.
3. The method of claim 1 , wherein the dopants comprise boron, phosphorous, arsenic, germanium, carbon, fluorine, indium, or a combination thereof.
4. The method of claim 1 , wherein implanting dopants into the semiconductor fin causes twin plane defects in the semiconductor fin.
5. The method of claim 4 , wherein the capping layer is grown over the twin plane defects.
6. The method of claim 1 further comprising:
forming a gate dielectric on the capping layer; and
forming a gate electrode on the gate dielectric.
7. The method of claim 1 , wherein a bottom surface of the capping layer adjoins a top surface of the isolation region.
8. The method of claim 1 further comprising:
after implanting dopants into the semiconductor fin and before recessing the isolation region, performing an anneal process on the semiconductor fin.
9. The method of claim 1 further comprising:
before homoepitaxially growing the capping layer, performing a dry etch process on the semiconductor fin.
10. A method comprising:
patterning a substrate to form a fin, the patterning forming a top surface and sidewalls of the fin, the top surface and the sidewalls of the fin having a same material composition;
forming an isolation region over the substrate, the isolation region surrounding the fin;
implanting dopants into the fin;
after implanting dopants into the fin, etching the isolation region to expose a first portion of the fin;
treating the first portion of the fin with a dry etch process; and
after treating the first portion of the fin, homoepitaxially growing a capping layer from the top surface and the sidewalls of the first portion of the fin, wherein portions of the capping layer disposed on the sidewalls of the first portion of the fin have a first thickness proximal the substrate and a second thickness distal the substrate greater than the first thickness.
11. The method of claim 10 further comprising:
forming a gate dielectric on the capping layer; and
forming a gate electrode on the gate dielectric.
12. The method of claim 11 further comprising:
forming a source region in the fin; and
forming a drain region in the fin, the source region being on an opposite side of the gate electrode than the drain region, the capping layer extending across the top surface of the fin from the source region to the drain region.
13. The method of claim 10 , wherein a bottom surface of the capping layer adjoins a top surface of the isolation region.
14. The method of claim 10 , wherein implanting dopants into the fin causes twin plane defects in the fin, the capping layer being grown over the twin plane defects.
15. The method of claim 10 further comprising:
before patterning the substrate to form the fin, doping the substrate with dopants; and
patterning the substrate to form a second fin on the doped substrate, before implanting dopants into the fin, the isolation region surrounding the second fin, the isolation region contacting opposite sidewalls of both the fin and the second fin.
16. The method of claim 10 further comprising:
after implanting dopants into the fin and before etching the isolation region, performing an anneal process on the fin.
17. A method comprising:
patterning a substrate to form a fin, the patterning forming a top surface and sidewalls of the fin, the top surface and the sidewalls of the fin having a same material composition;
forming an isolation region on the substrate, the isolation region surrounding the fin;
implanting the fin with dopants, the implanting the fin with dopants causing twin plane defects in the fin;
after implanting dopants into the fin, recessing the isolation region to expose an upper portion of the fin;
homoepitaxially growing a capping layer from the top surface and the sidewalls of the fin, the capping layer being grown over the twin plane defects; and
after epitaxially growing the capping layer, forming a gate structure on the capping layer, wherein the gate structure is in contact with at least a portion of the fin exposed by the capping layer.
18. The method of claim 17 further comprising:
forming a source region in the fin; and
forming a drain region in the fin, the gate structure being interposed between the drain region and the source region, the capping layer extending across the top surface of the fin from the source region to the drain region.
19. The method of claim 17 , wherein a portion of the capping layer distal the substrate has a thickness greater than a portion of the capping layer proximal the substrate.
20. The method of claim 19 , wherein the capping layer has a thickness from 2 nm to 6 nm.