Methods for forming a semiconductor arrangement with multiple-height fins and substrate trenches
Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. An etch sequence is performed to form a first etched region over a planar region of a semiconductor arrangement. The first etched region exposes a planar structure, such as an alignment mark used for alignment during semiconductor fabrication. The etch sequence forms a second etched region over a semiconductor fin region of the semiconductor arrangement. In an embodiment, the etch sequence forms a first trench, a first fin nub and a first pillar in the semiconductor fin region, where the first trench is formed in a semiconductor substrate of the semiconductor fin region. A multi-depth STI structure is formed over at least one of the first trench, the first fin nub, or the first pillar.
1. A method for forming a semiconductor arrangement, comprising:
forming a plurality of semiconductor fins, wherein:
a first fin of the plurality of semiconductor fins has a first height,
a second fin of the plurality of semiconductor fins has a second height smaller than the first height,
a third fin of the plurality of semiconductor fins has a third height different than the second height, and
the second fin is between the first fin and the third fin;
forming a layer over the plurality of semiconductor fins;
forming a first recess in the layer over the second fin and the third fin; and
etching the second fin, the third fin, and a portion of a substrate underlying the second fin after forming the first recess, wherein a first trench is defined in the portion of the substrate underlying the second fin due to the etching.
2. The method of claim 1 , comprising forming a planar structure on the substrate adjacent the plurality of semiconductor fins prior to forming the layer over the plurality of semiconductor fins.
3. The method of claim 2 , wherein the planar structure is at least one of an alignment mark or an overlay mark.
4. The method of claim 2 , wherein forming the layer comprises further forming the layer over the planar structure.
5. The method of claim 4 , comprising forming a second recess in the layer over the planar structure.
6. The method of claim 5 , wherein the first recess and the second recess are formed concurrently.
7. The method of claim 5 , comprising etching the planar structure after forming the second recess to define a second trench.
8. The method of claim 7 , comprising forming an isolation layer within the first trench, the second trench, and over a top surface of the substrate between the first fin and the third fin.
9. The method of claim 7 , wherein the second fin, the third fin, and the planar structure are etched concurrently.
10. The method of claim 1 , wherein:
forming the first recess comprises performing a first etch using a first etch chemistry, and
etching the second fin, the third fin, and the portion of the substrate underlying the second fin comprises performing a second etch using a second etch chemistry different than the first etch chemistry.
11. The method of claim 1 , wherein the plurality of semiconductor fins comprises a fourth fin having the second height and wherein the first recess is not formed over the fourth fin.
12. The method of claim 1 , comprising forming an isolation layer within the first trench and over a top surface of the substrate between the first fin and the third fin.
13. The method of claim 12 , wherein forming the isolation layer comprises further forming the isolation layer over the top surface of the third fin.
14. The method of claim 12 , comprising:
forming a gate oxide layer over a portion of the first fin not concealed by the isolation layer; and
forming a gate structure over the gate oxide layer.
15. A method for forming a semiconductor arrangement, comprising:
forming a plurality of semiconductor fins, wherein:
a first fin of the plurality of semiconductor fins has a first height, and
a second fin of the plurality of semiconductor fins has a second height smaller than the first height;
forming a layer over the plurality of semiconductor fins;
forming a first recess in the layer over the second fin; and
etching the second fin and a portion of a substrate underlying the second fin after forming the first recess, wherein:
a trench is defined in the portion of the substrate underlying the second fin, and
the first fin maintains the first height after the etching.
16. The method of claim 15 , comprising forming an isolation layer within the trench and over a top surface of the substrate between the first fin and the trench.
17. The method of claim 16 , wherein the isolation layer surrounds a portion of the first fin.
18. The method of claim 17 , comprising:
forming a gate oxide layer over a portion of the first fin that is not surrounded by the isolation layer; and
forming a gate structure over the gate oxide layer.
19. The method of claim 15 , wherein:
a third fin of the plurality of semiconductor fins has a third height different than the second height, and
the method comprises etching the third fin concurrently with etching the second fin to reduce a height of the third fin.
20. A method for forming a semiconductor arrangement, comprising:
forming a plurality of semiconductor fins, wherein:
a first fin of the plurality of semiconductor fins has a first height, and
a second fin of the plurality of semiconductor fins has a second height smaller than the first height;
forming a layer over the plurality of semiconductor fins;
forming a first recess in the layer over the second fin; and
etching the first fin, the second fin, and a portion of a substrate underlying the second fin after forming the first recess, wherein:
a trench is defined in the portion of the substrate underlying the second fin, and
the first fin has a third height after the etching, the third height less than the first height.