IP Library Granted Patent US 10,153,770
Granted Patent B2
US 10,153,770 · App. 15/369,674 · Granted Dec 11, 2018

Programmable input/output circuit

Inventors: Timothy John Williams (Bellevue, WA); David G. Wright (Woodinville, WA); Gregory John Verge (Lynwood, WA); Bruce E. Byrkett (Preston, WA)
Assignee: Cypress Semiconductor Corporation
H03K19/017581G06F13/28G11C7/1057G11C7/1084
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Quick Facts
Patent No.
US 10,153,770
App. No.
15/369,674
Filed
Dec 5, 2016
Granted
Dec 11, 2018
Kind
B2
Art Unit
2844
USPC
326/38
Abstract

A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the IO pads.

Claims (8)

1. A system, comprising:

a processing system disposed on a first integrated circuit, the processing system comprising a processor, a storage device, and a system input/output (I/O); and

an intermediate circuit to couple to the system I/O and disposed outside of the processing system on a second integrated circuit, the intermediate circuit including, a terminal configured to receive a supply voltage, and a circuit I/O pin, wherein the circuit I/O pin is configured to receive a first analog signal from a first device and a second analog signal from second device, the first and second devices each disposed outside of the second integrated circuit of the intermediate circuit wherein the intermediate circuit is configured determine a logic level of the first analog signal using a first reference voltage and determine a logic level of the second analog signal using a second reference voltage.

2. The system of claim 1 , wherein the device comprises a peripheral device configured to provide an input signal to the circuit I/O pin and receive an output signal from the circuit I/O pin.

3. The system of claim 1 , wherein the circuit I/O pin is configured to receive a first signal having a first voltage level and second signal having a second voltage level.

4. The system of claim 1 , wherein each of the first device and the second device is a peripheral device including circuitry configured to perform a function responsive to a command from the processing system.

5. The system of claim 1 , wherein the intermediate circuit comprises one or more components that are powered by the supply voltage.

6. The system of claim 1 , wherein the intermediate circuit is configured to alternately switch between using the first reference voltage and using the second reference voltage during operation.

Assignments (5)
MERGER Recorded Nov 14, 2025
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 073571/0456 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
PATENT SECURITY AGREEMENT Recorded Apr 25, 2017
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 042326/0396 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 21, 2017
From: WILLIAMS, TIMOTHY J.; WRIGHT, DAVID G.; VERGE, GREGORY J.; BYRKETT, BRUCE E.
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 041324/0940 →
Continuity (8)
Continuation 14690106 · Apr 17, 2015
Continuation 14054657 · Oct 15, 2013
Continuation 13427264 · Mar 22, 2012
Continuation 12753657 · Apr 2, 2010
Provisional Application 61175586 · May 5, 2009
Provisional Application 61175856 · May 6, 2009
Provisional Application 61176933 · May 10, 2009
Related Publication 20170194963A1 · Jul 6, 2017