Display device and electronic device including the same
One embodiment of the present invention provides a highly reliably display device in which a high mobility is achieved in an oxide semiconductor. A first oxide component is formed over a base component. Crystal growth proceeds from a surface toward an inside of the first oxide component by a first heat treatment, so that a first oxide crystal component is formed in contact with at least part of the base component. A second oxide component is formed over the first oxide crystal component. Crystal growth is performed by a second heat treatment using the first oxide crystal component as a seed, so that a second oxide crystal component is formed. Thus, a stacked oxide material is formed. A transistor with a high mobility is formed using the stacked oxide material and a driver circuit is formed using the transistor.
1. A display device comprising:
a first substrate comprising a top surface;
a second substrate;
a sealant;
a first silicon nitride layer over the first substrate;
a first silicon oxide layer on and in contact with the first silicon nitride layer;
a second silicon oxide layer over the first silicon oxide layer;
a second silicon nitride layer on and in contact with the second silicon oxide layer;
a scan line driver circuit over the first substrate;
an FPC affixed to the first substrate and in electrical contact with the scan line driver circuit; and
a pixel portion over the first substrate and adjacent to the scan line driver circuit, the pixel portion comprising:
a gate electrode layer over the first substrate, and comprising a top surface and a side surface, the side surface having an inclination with respect to the top surface of the first substrate;
an oxide semiconductor layer over the first substrate with the gate electrode layer interposed therebetween, and comprising a first portion facing the top surface of the gate electrode layer, and a second portion inclined in response to the inclination of the side surface of the gate electrode layer;
a gate insulating layer between the gate electrode layer and the oxide semiconductor layer, the gate insulating layer comprising the first silicon nitride layer and the first silicon oxide layer, the first silicon oxide layer being in direct contact with the oxide semiconductor layer;
a source electrode layer and a drain electrode layer on and in direct contact with the oxide semiconductor layer and below the second silicon oxide layer and the second silicon nitride layer;
an organic insulating layer on and in direct contact with the second silicon nitride layer;
a pixel electrode over the organic insulating layer and in electrical contact with the oxide semiconductor layer via an opening in the organic insulating layer, in the second silicon nitride layer, and in the second silicon oxide layer; and
a liquid crystal layer over the pixel electrode and the organic insulating layer,
wherein the scan line driver circuit and the pixel portion are sealed together in a volume defined by the first substrate, the sealant, and the second substrate,
wherein the oxide semiconductor layer has crystallinity, and
wherein c-axis of crystals of the oxide semiconductor layer are substantially perpendicular to a surface of the oxide semiconductor layer in both the first portion and the second portion.
2. A display device comprising:
a first substrate comprising a top surface;
a second substrate;
a sealant;
a first silicon nitride layer over the first substrate;
a first silicon oxide layer on and in contact with the first silicon nitride layer;
a second silicon oxide layer over the first silicon oxide layer;
a second silicon nitride layer on and in contact with the second silicon oxide layer;
a scan line driver circuit over the first substrate;
an FPC affixed to the first substrate and in electrical contact with the scan line driver circuit; and
a pixel portion over the first substrate and adjacent to the scan line driver circuit, the pixel portion comprising:
a gate electrode layer over the first substrate, and comprising a top surface and a side surface, the side surface having an inclination with respect to the top surface of the first substrate;
an oxide semiconductor layer over the first substrate with the gate electrode layer interposed therebetween, and comprising a first portion facing the top surface of the gate electrode layer, and a second portion inclined in response to the inclination of the side surface of the gate electrode layer;
a gate insulating layer between the gate electrode layer and the oxide semiconductor layer, the gate insulating layer comprising the first silicon nitride layer and the first silicon oxide layer, the first silicon oxide layer being in direct contact with the oxide semiconductor layer;
a source electrode layer and a drain electrode layer on and in direct contact with the oxide semiconductor layer and below the second silicon oxide layer and the second silicon nitride layer;
an organic insulating layer on and in direct contact with the second silicon nitride layer;
a pixel electrode over the organic insulating layer and in electrical contact with the oxide semiconductor layer via an opening in the organic insulating layer, in the second silicon nitride layer, and in the second silicon oxide layer; and
a liquid crystal layer over the pixel electrode and the organic insulating layer,
wherein the source electrode layer and the drain electrode layer overlap with the gate electrode layer and are on and in direct contact with side end portions of the oxide semiconductor layer,
wherein the scan line driver circuit and the pixel portion are sealed together in a volume defined by the first substrate, the sealant, and the second substrate,
wherein the oxide semiconductor layer has crystallinity, and
wherein c-axis of crystals of the oxide semiconductor layer are substantially perpendicular to a surface of the oxide semiconductor layer in both the first portion and the second portion.
3. A display device comprising:
a first substrate comprising a top surface;
a second substrate;
a sealant;
a first silicon nitride layer over the first substrate;
a first silicon oxide layer on and in contact with the first silicon nitride layer;
a second silicon oxide layer over the first silicon oxide layer;
a second silicon nitride layer on and in contact with the second silicon oxide layer;
a scan line driver circuit over the first substrate;
an FPC affixed to the first substrate and in electrical contact with the scan line driver circuit; and
a pixel portion over the first substrate and adjacent to the scan line driver circuit, the pixel portion comprising:
a gate electrode layer over the first substrate, and comprising a top surface and a side surface, the side surface having an inclination with respect to the top surface of the first substrate;
an oxide semiconductor layer over the first substrate with the gate electrode layer interposed therebetween, and comprising a first portion facing the top surface of the gate electrode layer, and a second portion inclined in response to the inclination of the side surface of the gate electrode layer;
a gate insulating layer between the gate electrode layer and the oxide semiconductor layer, the gate insulating layer comprising the first silicon nitride layer and the first silicon oxide layer, the first silicon oxide layer being in direct contact with the oxide semiconductor layer;
a source electrode layer and a drain electrode layer on and in direct contact with the oxide semiconductor layer and below the second silicon oxide layer and the second silicon nitride layer;
an organic insulating layer on and in direct contact with the second silicon nitride layer;
a pixel electrode over the organic insulating layer and in electrical contact with the oxide semiconductor layer via an opening in the organic insulating layer, in the second silicon nitride layer, and in the second silicon oxide layer; and
a liquid crystal layer over the pixel electrode and the organic insulating layer,
wherein the scan line driver circuit and the pixel portion are sealed together in a volume defined by the first substrate, the sealant, and the second substrate,
wherein the oxide semiconductor layer has a stacked structure and includes a c-axis aligned crystal layer, and
wherein c-axis of crystals of the oxide semiconductor layer are substantially perpendicular to a surface of the oxide semiconductor layer in both the first portion and the second portion.
4. The display device according to claim 3 ,
wherein the oxide semiconductor layer comprises a first oxide component and a second oxide component.
5. The display device according to claim 3 ,
wherein the oxide semiconductor layer comprises a first oxide component and a second oxide component,
wherein an atomic ratio of the first oxide component and an atomic ratio of the second oxide component are different from each other.
6. The display device according to claim 3 ,
wherein the oxide semiconductor layer comprises a first oxide component and a second oxide component,
wherein the second oxide component is on and in contact with the first oxide component, and
wherein the second oxide component is structured by crystal growth using the first oxide component as seed.
7. The display device according to claim 3 ,
wherein the source electrode layer and the drain electrode layer overlap with the gate electrode layer and are on and in direct contact with side end portions of the oxide semiconductor layer.
8. The display device according to claim 1 ,
wherein the oxide semiconductor layer comprises indium, gallium, and zinc.
9. The display device according to claim 2 ,
wherein the oxide semiconductor layer comprises indium, gallium, and zinc.
10. The display device according to claim 3 ,
wherein the oxide semiconductor layer comprises indium, gallium, and zinc.
11. The display device according to claim 1 , further comprising a counter electrode,
wherein the counter electrode is over the liquid crystal layer.
12. The display device according to claim 2 , further comprising a counter electrode,
wherein the counter electrode is over the liquid crystal layer.
13. The display device according to claim 3 , further comprising a counter electrode,
wherein the counter electrode is over the liquid crystal layer.