Semiconductor memory device with late write feature

1. A semiconductor memory device comprising:

a base chip;

a first memory chip which is stacked over the base chip; and

a first through via which is provided between the base chip and the first memory chip, and is used for transmitting read data and write data,

wherein the base chip has

an external interface circuit which externally receives/transmits the write data and the read data, and

a first late write control circuit which has a plurality of first registers storing the write data supplied externally through the external interface circuit and transferring a previous write data stored therein in response to a write command,

wherein the first memory chip has

a memory cell array which has a plurality of memory cells arranged in a matrix, and

a plurality of second late write control circuits, each of which second late write control circuit has at least a second register storing the write data supplied from the first registers through the first through via and transferring the previous write data stored therein, and writes the previous write data output from the second register into a target memory cell for writing,

wherein the first memory chip includes a plurality of memory banks of a same channel, a second late write control circuit is provided correspondingly to each one of the memory banks, a number of the first registers corresponds to a number of the memory banks, and

wherein one of the first registers is selected, based on a bank address, and the data stored in the selected first register is transferred.

2. The semiconductor memory device according to claim 1 , further comprising a second memory chip which is stacked over the base chip, and wherein each of the first and second memory chips includes a plurality of memory banks of a same channel, formed of the memory cell array, and a plurality of the second late write control circuits corresponding to the memory cell array.

3. The semiconductor memory device according to claim 1 ,

wherein each second late write control circuit includes a plurality of pipelined second registers.

4. The semiconductor memory device according to claim 1 , wherein each first late write control circuit incorporates a cache memory as the first register.

5. The semiconductor memory device according to claim 1 ,

wherein each first late write control circuit outputs write data stored in the first register as read data, when there is coincidence between an address signal corresponding to the write data stored in the first register and an externally supplied address signal for data reading.

6. The semiconductor memory device according to claim 5 ,

wherein each second late write control circuit outputs write data stored in the second register as read data, when there is coincidence between an address signal corresponding to the write data stored in the second register and an externally supplied address signal for data reading.

7. The semiconductor memory device according to claim 5 , further comprising

a gating circuit which stops supplying the address signal for data reading to the memory cell array, when there is coincidence between an address signal corresponding to write data stored in the first register and an externally supplied address signal for data reading.

8. The semiconductor memory device according to claim 1 ,

wherein the base chip further includes an arithmetic unit, which generates an arithmetic value in place of write data and executes a predetermined arithmetic operation based on the arithmetic value stored in the first register and data read from a target memory cell for writing-back, and

wherein an arithmetic result by the arithmetic unit is stored in the first register as new write data.

9. The semiconductor memory device according to claim 1 , further comprising a second through via provided between the base chip and the first memory chip, and used for transmitting an address signal,

wherein each first late write control circuit further comprises a first address register storing an address signal supplied externally through the external interface circuit and transferring a previous address signal stored therein in response to the write command, and

wherein each second late write control circuit further comprises a second address register storing the address signal supplied from the first address register through the second through via and transferring a previous address signal stored therein in response to a succeeding write command.

10. A semiconductor memory device, comprising:

a base chip;

a first memory chip which is stacked over the base chip; and

a first through via provided between the base chip and the first memory chip,

wherein the base chip comprises:

an external interface circuit which externally receives/transmits write data and read data; and

a first late write control circuit comprising a plurality of first registers storing the write data supplied externally through the external interface circuit and transferring previous write data stored therein in response to a write command, and

wherein the first memory chip comprises:

a memory cell array comprising a plurality of memory cells arranged in a matrix; and

a plurality of second late write control circuits, each of the second late write control circuits comprising at least a second register storing a first write data supplied from the first register through the first through via, transferring previous second write data stored therein, and writing the second write data output from the second register into a target memory cell,

wherein the first memory chip includes a plurality of memory banks of a same channel, one each of the second late write control circuits is provided for a corresponding one of the memory banks, a number of the first registers corresponding to a number of the memory banks, and

wherein one of the first registers is selected, based on a bank address, and the data stored in the selected first register is transferred.