Semiconductor structure and manufacturing method thereof
The present disclosure provides a method of manufacturing a structure. The method comprises: providing a substrate; forming an interconnect layer over the substrate; forming a plurality of conductive pads over the interconnect layer; forming conductive pillars over the interconnect layer; disposing a first semiconductor die over the conductive pads, the semiconductor die being spaced apart from the conductive pillars; and bonding a second semiconductor die with the conductive pillars.
1. A method of manufacturing a semiconductor package, the method comprising:
providing a substrate;
forming an interconnect layer over the substrate;
forming a plurality of conductive pads over the interconnect layer;
forming conductive pillars over the interconnect layer;
disposing a first semiconductor die over the conductive pads, the first semiconductor die being spaced apart from the conductive pillars;
bonding a second semiconductor die with the conductive pillars; and
thinning the interconnect layer to expose a conductive portion of the interconnect layer.
2. The method of claim 1 , further comprising providing an adhesive layer over the substrate before forming the interconnect layer.
3. The method of claim 1 , further comprising:
forming a connector electrically connecting the interconnect layer at the conductive portion.
4. The method of claim 1 , further comprising:
encapsulating the first semiconductor die, the conductive pillars and the conductive pads; and
exposing a top surface of the first semiconductor die.
5. The method of claim 1 , further comprising filling a gap between the first semiconductor die and the second semiconductor die.
6. The method of claim 5 , further comprising encapsulating the second semiconductor die laterally.
7. The method of claim 1 , further comprising electrically connecting an integrated passive device to the interconnect layer on a same side of the first semiconductor die.
8. The method of claim 1 , further comprising bonding an integrated passive device and a connector to the interconnect layer on a same side opposite to the first semiconductor die.
9. The method of claim 1 , further comprising performing a first test against the interconnect layer before disposing the first semiconductor die over the conductive pads.
10. The method of claim 1 , further comprising performing a second test against the interconnect layer and the first semiconductor die before bonding the second semiconductor die with the conductive pillars.
11. A method of manufacturing a semiconductor package, the method comprising:
providing a first substrate;
forming an interconnect layer over the first substrate;
forming a plurality of conductive pads over the interconnect layer, the plurality of conductive pads comprising at least one test pad;
bonding a first semiconductor die with the plurality of conductive pads;
disposing a second substrate over the first semiconductor die on a side opposite to the first substrate;
removing the first substrate from a first surface of the interconnect layer; and
forming a connector on the first surface.
12. The method of claim 11 , further comprising forming conductive pillars on the interconnect layer before disposing the second substrate over the first semiconductor die.
13. The method of claim 12 , further comprising:
removing the second substrate;
exposing the conductive pillars; and
bonding a second semiconductor die with the conductive pillars.
14. The method of claim 13 , further comprising performing a singulation operation after the operation of bonding the second semiconductor die with the conductive pillars.
15. The method of claim 11 , wherein at least one of the first substrate and the second substrate is selected from glass, ceramic or silicon.
16. The method of claim 11 , further comprising performing a first test against the interconnect layer through the at least one test pad over the interconnect layer.
17. The method of claim 11 , further comprising bonding an integrated passive device to the interconnect layer on a side opposite to the first semiconductor die.
18. A method of manufacturing a semiconductor package, the method comprising:
providing a first substrate;
forming an interconnect layer over the first substrate;
forming a plurality of conductive pads over the interconnect layer, the plurality of conductive pads comprising a test pad;
performing a first test against the interconnect layer through the test pad;
bonding a first semiconductor die with the plurality of conductive pads in response to the interconnect layer as passing the first test;
encapsulating the first semiconductor die and the plurality of conductive pads with an encapsulating material; and
bonding a second semiconductor die with the encapsulated first semiconductor die.
19. The method of claim 18 , wherein encapsulating the first semiconductor die and the plurality of conductive pads is performed in response to a result of a second test against the semiconductor die and the plurality of conductive pads as being successful.
20. The method of claim 18 , wherein the second semiconductor die is electrically coupled to the interconnect layer through a conductive pillar encapsulated by the encapsulating material adjacent to the first semiconductor die.