Relative timed clock gating cell
Technology is described for a relative timed clock gated cell. In one example, the relative timed clock gated cell includes a trigger latch and a data clock latch. The trigger latch includes a clock input coupled to a trigger line for transmitting a trigger signal. The trigger latch is configured to generate a data clock signal on an output. The trigger signal is based on a clock signal. The data clock latch includes a clock input coupled to the output of the trigger latch that latches a data input of the data clock latch based on the data clock signal. Various other computing circuitries and methods are also disclosed.
1. A relative timed clock gated circuit comprising circuitry configured to:
activate the circuitry based on a trigger clock signal, wherein the trigger clock signal is generated from a logical ANDing function of an asynchronous trigger signal with a clock signal, and the asynchronous trigger signal has a fewer number of cycles than the clock signal;
trigger an action based on the trigger clock signal, wherein the relative timed clock gated circuit includes a relative timed clock gated state machine, and the action includes a transitioning to a next state or incrementing counter to count cycles of the trigger clock signal;
reset the relative timed clock gated state machine to a default state based on a second input; and
count multi-cycle clock events within a state after the asynchronous trigger signal is asserted.
2. The circuitry of claim 1 , wherein the clock signal is a delayed clock signal that is phase shifted from a received clock signal.
3. The circuitry of claim 2 , further comprising:
a trigger latch configured to receive the received clock signal and to output the asynchronous trigger signal to a functional circuit block that performs the logical ANDing function.
4. The circuitry of claim 1 , further comprising:
a data latch configured to receive the trigger clock signal at a clock input of the data latch and to output a previously latched value in response to receiving the trigger clock signal.
5. A relative timed clock gated circuit, the circuit comprising:
a first latch that includes
a first clock input that receives a clock signal, and
a first output that outputs an asynchronous trigger signal, the asynchronous trigger signal having a fewer number of cycles than the clock signal;
a functional circuit block that includes a logical ANDing circuit that generates a trigger clock signal based on the asynchronous trigger signal and the clock signal; and
a second latch that includes a second clock input coupled to the functional circuit block and that is triggered in response to receiving the trigger clock signal at the second clock input wherein the second latch is part of a relative timed clock gated state machine and, when triggered in response to receiving the trigger clock signal, the relative timed clock gated state machine includes transitioning to a next state or incrementing a counter to count cycles of the trigger clock signal, and
wherein the circuit is further configured to:
reset the relative timed clock gated state machine to a default state based on a second input; and
count multi-cycle clock events within a state after the asynchronous trigger signal is asserted.
6. The relative timed clock gated circuit of claim 5 , wherein the clock signal is a delayed clock signal that is phase shifted from a received clock signal, and the logical ANDing circuit generates the trigger clock signal based on a logical ANDing of the asynchronous trigger signal and the delayed clock signal.
7. A method of implementing a relative timed clock gated circuit, the method comprising:
generating a trigger clock signal from a logical ANDing function of an asynchronous trigger signal with a clock signal, the asynchronous trigger signal having a fewer number of cycles than the clock signal; and
triggering an action based on the trigger clock signal, wherein the relative timed clock gated circuit includes a relative timed clock gated state machine, and triggering the action includes incrementing a counter to count cycles of the trigger clock signal.
8. The method of claim 7 , further comprising:
providing the clock signal as a delayed clock signal that is phase shifted from a received clock signal that is received by the relative timed clock gated circuit.
9. The method of claim 8 , further comprising:
receiving, by a trigger latch, the received clock signal; and
outputting, by the trigger latch, the asynchronous trigger signal to a functional circuit block that performs the logical ANDing function.
10. The method of claim 7 , further comprising:
receiving, by a data latch, the trigger clock signal at a clock input of the data latch; and
outputting, by the data latch, a previously latched value in response to receiving the trigger clock signal.
11. The method of claim 7 , wherein the relative timed clock gated circuit includes a relative timed clock gated state machine, and triggering the action includes transitioning to a next state.
12. The method of claim 7 , further comprising:
resetting the relative timed clock gated state machine to a default state based on a second input; and
counting multi-cycle clock events within a state after the asynchronous trigger signal is asserted.