IP Library Granted Patent US 9,972,623
Granted Patent B1
US 9,972,623 · App. 15/375,177 · Granted May 15, 2018

Semiconductor device including barrier layer and manufacturing method thereof

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,972,623
App. No.
15/375,177
Granted
May 15, 2018
Kind
B1
Abstract

A manufacturing method of a semiconductor device includes the following steps. A barrier layer is formed in a first region and a second region of a semiconductor substrate. The barrier layer formed in the first region is thinned before a step of forming a first work function layer on the barrier layer. The first work function layer formed on the first region is then removed. The process of thinning the barrier layer in the first region and the process of removing the first work function layer in the first region are performed separately for ensuring the coverage of the first work function layer in the second region. The electrical performance of the semiconductor device and the uniformity of the electrical performance of the semiconductor device may be improved accordingly.

Claims (11)

1. A semiconductor device, comprising:

a first conductivity type transistor comprising:

a first gate structure comprising a first barrier layer; and

a first part of a first conductivity type work function layer; and

a second conductivity type transistor disposed adjacent to the first conductivity type transistor, wherein the second conductivity type transistor comprises:

a second gate structure, wherein the first gate structure is directly connected to the second gate structure, and the second gate structure comprises:

a second barrier layer, wherein the first barrier layer is thinner than the second barrier layer, the first barrier layer and the second barrier layer are directly connected with each other, and a step structure is formed at a juncture of the first barrier layer and the second barrier layer; and

a second conductivity type work function layer disposed on the second barrier layer and a part of the first barrier layer, wherein the second conductivity type work function layer covers the step structure; and

a second part of the first conductivity type work function layer, wherein the first part of the first conductivity type work function layer is directly connected with the second part of the first conductivity type work function layer.

2. The semiconductor device of claim 1 , wherein the first part of the first conductivity type work function layer is disposed on the first barrier layer, and the second part of the first conductivity type work function layer is disposed on the second conductivity type work function layer.

3. The semiconductor device of claim 1 , wherein the first conductivity type transistor comprises an N type transistor, the second conductivity type transistor comprises a P type transistor, and the second conductivity type work function layer comprises a P type work function layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2016
From: LIN, CHUN-HAO; HSIEH, SHOU-WEI; CHEN, HSIN-YU
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 040704/0708 →