Semiconductor device and method for fabricating the same

1. A method for fabricating a semiconductor device, comprising:

providing a semiconductor substrate having a first region and a second region;

forming a plurality of first semiconductor fins in the first region and a plurality of second semiconductor fins in the second region;

forming a first solid-state dopant source layer within the first region on the semiconductor substrate;

forming a first insulating buffer layer on the first solid-state dopant source layer;

forming a second solid-state dopant source layer within the second region on the semiconductor substrate;

forming a second insulating buffer layer on the second solid-state dopant source layer and on the first insulating buffer layer; and

forming a first fin bump in the first region between the first semiconductor fins and a second bump in the second region between the second semiconductor fins, wherein the first fin bump comprises a first sidewall spacer and the second bump comprises a second sidewall spacer, wherein the first sidewall spacer has a structure that is different from that of the second sidewall spacer, and wherein the first sidewall spacer does not cover a top surface of the first fin bump, and the second sidewall spacer does not cover a top surface of the second fin bump.

2. The method for fabricating a semiconductor device according to claim 1 , wherein before forming the second solid-state dopant source layer within the second region on the semiconductor substrate, the method further comprises:

masking the first region; and

removing the first solid-state dopant source layer and the first insulating buffer layer from the second region, to thereby expose the second semiconductor fins in the second region.

3. The method for fabricating a semiconductor device according to claim 1 , wherein forming the second solid-state dopant source layer within the second region on the semiconductor substrate further comprises:

depositing the second solid-state dopant source layer on the first region and the second region in a blanket manner;

masking the second region; and

removing the second solid-state dopant source layer from the first region to thereby expose the first insulating buffer layer within the first region.

4. The method for fabricating a semiconductor device according to claim 1 , further comprising:

forming a dielectric layer on the second insulating buffer layer, the first fin bump, and the second fin bump;

recessing the dielectric layer, the second insulating buffer layer, the first solid-state dopant source layer, and the second solid-state dopant source layer to a level below a top surface of the plurality of first and second semiconductor fins, exposing protruding portions of each of the plurality of first and second semiconductor fins above sub-fin regions of each of the plurality of first and second semiconductor fins; and

driving dopants from the first and second solid-state dopant source layers into the sub-fin regions of each of the plurality of first and second semiconductor fins.

5. The method for fabricating a semiconductor device according to claim 4 , further comprising:

forming a gate electrode traversing the protruding portions of each of the plurality of first and second semiconductor fins;

forming source and drain regions in the protruding portions of each of the plurality of first and second semiconductor fins, on either side of the gate electrode; and

cutting the gate electrode into gate segments.

6. The method for fabricating a semiconductor device according to claim 5 , wherein each of the gate segments has a gate edge that is partially overlapped with the first fin bump or the second fin bump when viewed from above.

7. The method for fabricating a semiconductor device according to claim 6 , wherein the gate edge does not completely overlap with the first fin bump or the second fin bump when viewed from above.

8. The method for fabricating a semiconductor device according to claim 1 , wherein the first solid-state dopant source layer comprises a borosilicate glass (BSG) layer.

9. The method for fabricating a semiconductor device according to claim 1 , wherein the second solid-state dopant source layer comprises a phosphosilicate glass (PSG) layer or an arsenic silicate glass (AsSG) layer.

10. The method for fabricating a semiconductor device according to claim 1 , wherein the first insulating buffer layer comprises silicon nitride.

11. The method for fabricating a semiconductor device according to claim 1 , wherein the second insulating buffer layer comprises silicon nitride.

12. The method for fabricating a semiconductor device according to claim 1 , wherein the first sidewall spacer comprises a residual portion of the first solid-state dopant source layer, a residual portion of the first insulating buffer layer, and a residual portion of the second insulating buffer layer.

13. The method for fabricating a semiconductor device according to claim 1 , wherein the second sidewall spacer comprises a residual portion of the second solid-state dopant source layer and a residual portion of the second insulating buffer layer.

14. A semiconductor device, comprising:

a semiconductor substrate having a first region and a second region;

a plurality of first semiconductor fins in the first region;

a plurality of second semiconductor fins in the second region;

a first solid-state dopant source layer within the first region on the semiconductor substrate,

a first insulating buffer layer on the first solid-state dopant source layer;

a second solid-state dopant source layer within the second region on the semiconductor substrate;

a second insulating buffer layer on the second solid-state dopant source layer and on the first insulating buffer layer;

a first fin bump in the first region; and

a second fin bump in the second region, wherein the first fin bump comprises a first sidewall spacer and the second fin bump comprises a second sidewall spacer, wherein the first sidewall spacer has a structure that is different from that of the second sidewall spacer, and wherein the first sidewall spacer does not cover a top surface of the first fin bump, and the second sidewall spacer does not cover a top surface of the second fin bump.

15. The semiconductor device according to claim 14 , wherein the first solid-state dopant source layer comprises a borosilicate glass (BSG) layer.

16. The semiconductor device according to claim 14 , wherein the second solid-state dopant source layer comprises a phosphosilicate glass (PSG) layer or an arsenic silicate glass (AsSG) layer.

17. The semiconductor device according to claim 14 , wherein the first insulating buffer layer comprises silicon nitride.

18. The semiconductor device according to claim 14 , wherein the second insulating buffer layer comprises silicon nitride.

19. The semiconductor device according to claim 14 , wherein the first sidewall spacer comprises a residual portion of the first solid-state dopant source layer, a residual portion of the first insulating buffer layer, and a residual portion of the second insulating buffer layer.

20. The semiconductor device according to claim 14 , wherein the second sidewall spacer comprises a residual portion of the second solid-state dopant source layer and a residual portion of the second insulating buffer layer.