IP Library Granted Patent US 10,283,475
Granted Patent B2
US 10,283,475 · App. 15/378,154 · Granted May 7, 2019

Power module assembly with dual substrates and reduced inductance

Inventors: Terence G. Ward (Waterford, MI); Constantin C. Stancu (Auburn Hills, MI); Marko Jaksic (Rochester Hills, MI)
Assignee: GM Global Technology Operations LLC
H01L24/27H01L23/528H01L23/5226H01L23/53214H01L23/53228H01L24/32H01L24/40H01L24/73H01L25/0655H01L25/072H01L25/50H01L24/33H01L24/48H01L24/83H01L2224/27505H01L2224/32151H01L2224/32227H01L2224/32245H01L2224/33181H01L2224/40227H01L2224/40491H01L2224/48227H01L2224/73215H01L2224/73221H01L2224/73263H01L2224/73265H01L2224/8309H01L2224/8384H01L2224/8484H01L2225/06527H01L2924/00014
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Quick Facts
Patent No.
US 10,283,475
App. No.
15/378,154
Granted
May 7, 2019
Kind
B2
Abstract

A power module assembly has a first substrate including a first layer, second layer and a third layer. The first layer is configured to carry a switch current flowing in a first direction. A second substrate is operatively connected to the first substrate and includes a fourth layer, fifth layer and a sixth layer. A conductive joining layer connects the third layer of the first substrate and the fourth layer of the second substrate. The conductive joining layer may be a first sintered layer. The third layer of the first substrate, the first sintered layer and the fourth layer of the second substrate are configured to function together as a unitary conducting layer carrying the switch current in a second direction substantially opposite to the first direction. The net inductance is reduced by a cancellation effect of the switch current going in opposite directions.

Claims (58)

1. A power module assembly comprising:

a first substrate including a first layer, second layer and a third layer, the first layer and the third layer being electrically conductive;

wherein the first layer is configured to carry a switch current flowing in a first direction;

wherein the second layer is an electrically insulating layer positioned between and configured to electrically isolate the first and the third layers;

a second substrate operatively connected to the first substrate and including a fourth layer, fifth layer and a sixth layer, the fourth layer and the sixth layer being electrically conductive;

wherein the fifth layer is an electrically insulating layer positioned between and configured to electrically isolate the fourth and the sixth layers;

a conductive joining layer connecting the third layer of the first substrate and the fourth layer of the second substrate;

a first semi-conductor stack operatively connected to the first layer at a first junction and a second semi-conductor stack operatively connected to the first layer at a third junction, such that the switch current flows from the first semi-conductor stack to the second semi-conductor stack;

an adjacent set of terminals, including a first terminal operatively connected to the first substrate and a second terminal operatively connected to the second substrate, the first terminal being adjacent to the second terminal;

a first flexible structure, a second flexible structure and an output node operatively connected to the first layer;

wherein the first flexible structure is positioned between the first semi-conductor stack and the adjacent set of terminals, and the second flexible structure is positioned between the second semi-conductor stack and the output node; and

wherein the third layer of the first substrate, the conductive joining layer and the fourth layer of the second substrate are configured to function together as a unitary conducting layer carrying the switch current in a second direction, the second direction being opposite to the first direction.

2. The assembly of claim 1 , wherein:

the conductive joining layer is a first sintered layer configured to join the first and second substrates via a sintering process, including urging micro particles of a predefined metal to coalesce into a solid form between the first and second substrates through heating at a temperature of 300 Celsius for one hour; and

the first sintered layer has a melting point of 900 degrees Celsius.

3. The assembly of claim 2 , wherein:

the first layer, the third layer, the fourth layer and the sixth layer are each composed of at least one of aluminum and copper; and

the second and the fifth layers are composed of at least one of silicon nitride, aluminum nitride and aluminum oxide.

4. The assembly of claim 1 , further comprising:

a first outer member electrically connected to the first layer at a second junction, the first outer member and the first flexible structure being placed on respective opposing sides of the first semi-conductor stack;

and

a second outer member electrically connected to the fourth layer at a fourth junction, the second outer member and the second flexible structure being placed on respective opposing sides of the second semi-conductor stack.

5. The assembly of claim 4 , wherein the switch current defines a switching loop between the first and second terminals, the switching loop being configured to extend:

from the first terminal to the first layer;

from the first layer to the first semi-conductor stack at the first junction;

from the first semi-conductor stack to the first outer member;

from the first outer member to the first layer at the second junction;

from the first layer to the second semi-conductor stack at the third junction;

from the second semi-conductor stack to the second outer member;

from the second outer member to the unitary conducting layer at the fourth junction; and

from the unitary conducting layer to the second terminal.

6. The assembly of claim 4 , wherein:

the first and second outer members have respective first, second and third sections, the respective first and third sections being parallel;

wherein the respective second sections are perpendicular to the respective first and third sections;

the first outer member has a first plurality of fingers separated by respective gaps; and

the second outer member has a second plurality of fingers separated by respective gaps.

7. The assembly of claim 4 , wherein the first semi-conductor stack includes:

a first semi-conductor device, a first metal layer, a second metal layer, the first semi-conductor device being sandwiched between the first and second metal layers;

a second sintered layer positioned between the first metal layer and the first semi-conductor device; and

a third sintered layer positioned between the second metal layer and the first semi-conductor device.

8. The assembly of claim 7 , wherein the first semi-conductor stack further includes:

a fourth sintered layer positioned between the first outer member and the first metal layer; and

a fifth sintered layer positioned between the second metal layer and the first layer of the first substrate.

9. The assembly of claim 4 , wherein the second semi-conductor stack includes:

a second semi-conductor device, a first metal layer, a second metal layer, the second semi-conductor device being sandwiched between the first and second metal layers;

a second sintered layer positioned between the first metal layer and the second semi-conductor device; and

a third sintered layer positioned between the second metal layer and the second semi-conductor device.

10. The assembly of claim 9 , wherein the second semi-conductor stack further includes:

a fourth sintered layer positioned between the second outer member and the first metal layer; and

a fifth sintered layer positioned between the second metal layer and the first layer of the first substrate.

11. The assembly of claim 1

wherein the first flexible structure has a plurality of co-extending layers, including a first gate layer, a second source layer and a third drain layer;

wherein the first gate layer, the second source layer and the third drain layer are electrically isolated from one another; and

wherein the first gate layer and the second source layer are configured such that a gate current flows in the first gate layer in a third direction and a source current flows in the second source layer in a fourth direction, the fourth direction being opposite to the third direction.

12. The assembly of claim 11 , wherein:

the switch current defines a switching loop through a first reference plane;

the gate current and the source current define a control loop in a second reference plane; and

the first reference plane is perpendicular to the second reference plane.

Assignments (2)
CONFIRMATORY LICENSE Recorded Jan 17, 2019
From: GENERAL MOTORS GLOBAL PROPULSION SYSTEMS
To: UNITED STATES DEPARTMENT OF ENERGY
Reel/Frame 048083/0621 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: WARD, TERENCE G.; STANCU, CONSTANTIN C.; JAKSIC, MARKO
To: GM GLOBAL TECHNOLOGY OPERATIONS LLC
Reel/Frame 040733/0040 →
Continuity (1)
Related Publication 20180166410A1 · Jun 14, 2018