Method and structure for finFET SRAM
A method for forming a semiconductor device includes providing a substrate structure having a plurality of semiconductor fins disposed on a substrate and a hard mask layer on the semiconductor fins. A first insulating material layer is formed covering the semiconductor fins, the hard masks, and the spaces between the semiconductor fins. Next, a first etch back process is performed to remove a top portion of the first insulating material layer to expose a portion of each of the semiconductor fins. Then dopants are implanted into remaining portions of the first insulating material layer and diffused into the semiconductor fins to form impurity regions. Next, a second etch back process is performed to remove a top portion of the remaining first insulating material layer to remove the implanted dopants in the first insulating material layer. Thereafter, a second insulating material layer is formed overlying the remaining first insulating material layer.
1. A method for forming a semiconductor device, comprising:
providing a substrate structure, the substrate structure comprising:
a substrate,
a plurality of semiconductor fins disposed on the substrate,
a hard mask layer disposed on each of the semiconductor fins, and
a first insulating material layer covering the plurality of semiconductor fins, the hard masks, and spaces between the semiconductor fins;
performing a first etch back process to remove a top portion of the first insulating material layer to expose a portion of each of the semiconductor fins;
implanting dopants into remaining portions of the first insulating material layer and causing dopants to diffuse into the semiconductor fins to form impurity regions having an upper surface and a lower surface;
performing a second etch back process to remove a top portion of the remaining portions of the first insulating material layer to remove the implanted dopants in the first insulating material layer;
forming a second insulating material layer overlying a remaining portion of the remaining portions of the first insulating material layer, the second insulating material layer having an upper surface lower than an upper surface of the semiconductor fins.
2. The method of claim 1 , wherein the substrate comprises a P-well and an N-well, and the plurality of semiconductor fins comprises a first set of fins overlying the P-well and configured for N-channel devices and a second set of fins disposed overlying the N-well and configured for P-channel devices.
3. The method of claim 2 , wherein forming impurity regions in each of the plurality of semiconductor fins comprises:
implanting P-type dopants into the remaining portions of the first insulating material layer adjacent to the first set of fins overlying the P-well and causing diffusion of the P-type dopants to form first impurity regions in the first set of fins overlying the P-well; and
implanting N-type dopants into the remaining portions of the first insulating material layer adjacent to the second set of fins overlying the N-well causing diffusion of the N-type dopants to form second impurity regions in the second set of fins.
4. The method of claim 3 , wherein:
the P-type dopants comprise boron ions or BF 2 ions; and
the N-type dopants comprise Arsenic ions.
5. The method of 3 , wherein:
the dopant concentration in the first impurity regions is higher than the dopant concentration in the P-well; and
the dopant concentration in the second impurity regions is higher than the dopant concentration in the N-well.
6. The method of claim 1 , wherein forming a second insulating material layer comprises:
forming a second insulating material layer overlying the plurality of semiconductor fins, the hard mask layers, and the remaining portions of the first insulating material layer;
planarizing the second insulating material layer such that the top surface the second insulating material layer is substantially aligned with the hard mask layers; and
etching the second insulating material layer to remove a portion of the second insulating material layer, such that an upper surface of a remaining portion of the second insulating material layer is higher than the upper surface of the impurity regions.
7. The method of claim 1 , wherein, after performing a second etch back process, an upper surface of the remaining portion of the remaining first insulating material layer is lower than the lower surface of the impurity regions.
8. The method of claim 1 , wherein the upper surface of the second insulating material layer is higher than the top surface of the impurity regions.
9. The method of claim 1 , wherein providing a substrate structure comprises:
providing an initial substrate that includes an initial semiconductor layer;
forming a patterned hard mask layer on the semiconductor layer;
etching the initial semiconductor layer using the patterned hard mask as an etch mask to form the plurality of semiconductor fins; and
depositing a first layer of insulating material to fill the spaces between the semiconductor fins and to cover each individual semiconductor fins, thereby forming the substrate structure.
10. The method of claim 1 , further comprising an annealing process to activate the dopants in the impurity regions.
11. The method of claim 1 , wherein:
the first insulating material layer is formed by Flowable Chemical Vapour Deposition (FCV); and
the second insulating material layer is formed by a high aspect ratio process (HARP) technology.