Forecasting wafer defects using frequency domain analysis

1. A method, comprising:

receiving defect information obtained from a test wafer, wherein the test wafer was fabricated according to an Integrated Circuit (IC) design layout;

receiving a plurality of first regions of interest (ROIs) based on the defect information, wherein the first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred;

performing a frequency domain analysis for the first ROIs; and

forecasting a wafer defect probability for the IC design layout based at least in part on the frequency domain analysis.

2. The method of claim 1 , further comprising, before the forecasting:

dividing the IC design layout into a plurality of second ROIs, wherein the second ROIs each correspond to a region of the IC design layout to be examined for the wafer defect probability;

performing the frequency domain analysis for the second ROIs; and

comparing a first result of the frequency domain analysis for the first ROIs with a second result of the frequency domain analysis for the second ROIs, wherein the forecasting is performed at least in part based on the comparing.

3. The method of claim 2 , wherein each of the first ROIs has a same size as each of the second ROIs.

4. The method of claim 2 , wherein the comparing comprises computing a cosine similarity between the first result and the second result.

5. The method of claim 2 , further comprising, before the forecasting:

receiving a plurality of third ROIs based on the defect information, wherein each of the third ROIs corresponds to a selected area of a respective one of the first ROIs;

dividing the IC design layout into a plurality of fourth ROIs; and

performing an image-based matching process between the first ROIs and the fourth ROIs, wherein the forecasting is performed at least in part based on the image-based matching process.

6. The method of claim 5 , wherein each of the third ROIs has a same size as each of the fourth ROIs.

7. The method of claim 5 , wherein the forecasting is further performed at least part based on the received defect information.

8. The method of claim 2 , wherein the forecasting comprises: predicting, for any one of the second ROIs, a numerical probability that the wafer defect will occur therein.

9. The method of claim 1 , wherein the performing of the frequency domain analysis comprises performing a Discrete Fourier Transform (DFT) to the first ROIs.

10. The method of claim 9 , wherein the performing the DFT generates both magnitude information and phase information, and wherein the method further comprises:

performing a Principal Component Analysis (PCA) using the magnitude information but not the phase information; and

extracting, based on the PCA, a principal component and a feature vector to represent the first ROIs as a result of the frequency domain analysis.

11. The method of claim 1 , wherein the forecasting is performed using a Naive Bayes Classification technique.

12. The method of claim 1 , further comprising: generating a weighted image corresponding to one of the first ROIs, wherein the weighted image contains a plurality of pixels each weighted based on its correlation with the wafer defect.

13. The method of claim 12 , wherein the generating the image is performed at least in part through an inverse Discrete Fourier Transform (DFT).

14. A method, comprising:

receiving defect information obtained from a test wafer, wherein the test wafer was fabricated according to an Integrated Circuit (IC) design layout;

receiving one or more first regions of interest (ROIs) based on the defect information, wherein the one or more first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred;

performing a first frequency domain analysis for the one or more first ROIs;

obtaining a first result based on the first frequency domain analysis;

performing a second frequency domain analysis for one or more second ROIs, wherein the one or more second ROIs each correspond to a region of the IC design layout to be examined for a wafer defect probability;

obtaining a second result based on the second frequency domain analysis;

determining a similarity between the first result and the second result; and

forecasting, based on the determining and using a Naive Bayes Classification technique, a defect probability for the one or more second ROIs.

15. The method of claim 14 , further comprising, before the forecasting:

receiving a plurality of third ROIs based on the defect information, wherein each of the third ROIs corresponds to a selected area of a respective one of the first ROIs; and

performing an image-based matching process between the first ROIs and one or more fourth ROIs, wherein each of the one or more fourth ROIs corresponds to a selected area of a respective one of the second ROIs, and wherein the forecasting is performed at least in part based on the image-based matching process.

16. The method of claim 15 , wherein the forecasting is further performed at least part based on the received defect information.

17. The method of claim 15 , wherein:

each of the first ROIs has a same size as each of the second ROIs; and

each of the third ROIs has a same size as each of the fourth ROIs.

18. The method of claim 14 , wherein the performing of the first frequency domain analysis and the performing of the second frequency domain analysis each comprises:

performing a Discrete Fourier Transform to generate both magnitude information and phase information;

performing a Principal Component Analysis (PCA) using the magnitude information but not the phase information; and

extracting, based on the PCA, a first principal component and a first feature vector as the first result and a second principal component and a second feature vector as the second result.

19. The method of claim 14 , further comprising: generating, at least in part by performing an inverse Discrete Fourier Transform (DFT), a weighted image corresponding to one of the first ROIs, wherein the weighted image contains a plurality of pixels each weighted based on its correlation with the wafer defect.

20. A method, comprising:

receiving defect information obtained from a test wafer, wherein the test wafer was fabricated according to an Integrated Circuit (IC) design layout;

receiving one or more first regions of interest (ROIs) based on the defect information, wherein the one or more first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred;

performing a first frequency domain analysis for the one or more first ROIs, wherein the first frequency domain analysis comprises a Discrete Fourier Transform (DFT) and a Principal Component Analysis (PCA);

obtaining a first principal component and a first feature vector as a result of the first frequency domain analysis;

performing a second frequency domain analysis for one or more second ROIs, wherein the one or more second ROIs each correspond to a region of the IC design layout to be examined for a wafer defect probability, wherein the first frequency domain analysis also comprises the DFT and the PCA;

obtaining a second principal component and a second feature vector as a result of the second frequency domain analysis;

computing a similarity between the first and second principal components and the first and second feature vectors; and

forecasting, based on the computed similarity, a defect probability for the one or more second ROIs, wherein the forecasting is performed at least in part using a Naive Bayes Classification technique.