Reference current generating circuitry, A/D converter, and wireless communication device
A reference current generating circuit has a variable current supply to output a reference current, delay circuitry to generate a reference clock by delaying a clock by a reference delay amount and a delay clock by delaying the clock depending on a current value of the reference current, a phase comparator to compare a phase of the reference clock with a phase of the delay clock to output a comparison result, and control circuitry to control the current value of the reference current based on the compared result.
1. A reference current generating circuit comprising:
a variable current supply to output a reference current;
delay circuitry to generate a reference clock by delaying a clock by a reference delay amount and a delay clock by delaying the clock depending on a current value of the reference current;
a phase comparator to compare a phase of the reference clock with a phase of the delay clock to output a comparison result; and
control circuitry to control the current value of the reference current based on the compared result,
wherein the control circuitry performs control so that a delay amount of the delay clock approaches the reference delay amount.
2. The reference current generating circuitry of claim 1 , wherein the delay circuitry comprises at least one delay unit to delay the clock depending on the current value of the reference current.
3. The reference current generating circuitry of claim 1 , wherein the reference delay amount is set depending on a cycle of the clock.
4. The reference current generating circuitry of claim 1 , wherein the clock is an operation clock of a discrete time signal processing circuitry.
5. The reference current generating circuitry of claim 1 , further comprising a pulse generator to generate a pulse based on a first delay clock and a second delay clock generated by the delay circuitry.
6. The reference current generating circuitry of claim 5 , wherein the pulse has a pulse width depending on a difference between a delay amount of the first delay clock and a delay amount of the second delay clock.
7. The reference current generating circuitry of claim 5 , wherein the pulse has a pulse width depending on a difference between a delay amount of the first delay clock and a delay amount of the second delay clock.
8. The reference current generating circuitry of claim 1 , further comprising a phase-locked loop to generate the clock by multiplying or dividing an operation clock of a discrete time signal processing circuitry.
9. An A/D converter comprising:
reference current generating circuitry; and
an operational amplifier to be supplied with the reference current generated by the reference current generating circuitry, as a driving current,
the reference current generating circuitry comprising:
a variable current source to output a reference current;
delay circuitry to generate a reference clock by delaying a clock by a reference delay amount and a delay clock by delaying the clock depending on a current value of the reference current;
a phase comparator to compare a phase of the reference clock with a phase of the delay clock to output a comparison result; and
control circuitry to control the current value of the reference current based on the compared result,
wherein the control circuitry performs control so that a delay amount of the delay clock approaches the reference delay amount.
10. The A/D converter of claim 9 , wherein the delay circuitry comprises at least one delay unit to delay the clock depending on the current value of the reference current.
11. The A/D converter of claim 9 , wherein the reference delay amount is set depending on a cycle of the clock.
12. The A/D converter of claim 9 , wherein the clock is an operation clock of a discrete time signal processing circuitry.
13. The A/D converter of claim 9 , further comprising a pulse generator to generate a pulse based on a first delay clock and a second delay clock generated by the delay circuitry.
14. The A/D converter of claim 9 , further comprising a phase-locked loop to generate the clock by multiplying or dividing an operation clock of a discrete time signal processing circuitry.
15. A wireless communication device comprising an A/D converter, the A/D converter comprising:
reference current generating circuitry; and
an operational amplifier to be supplied with the reference current generated by the reference current generating circuitry, as a driving current,
the reference current generating circuitry having:
a variable current supply to output a reference current;
delay circuitry to generate a reference clock by delaying a clock by a reference delay amount and a delay clock by delaying the clock depending on a current value of the reference current;
a phase comparator to compare a phase of the reference clock with a phase of the delay clock to output a comparison result; and
a control circuitry to control the current value of the reference current based on the comparison result,
wherein the control circuitry performs control so that a delay amount of the delay clock approaches the reference delay amount.
16. The wireless communication device of claim 15 , wherein the delay circuitry comprises at least one delay unit to delay the clock depending on the current value of the reference current.
17. The wireless communication device of claim 15 , wherein the reference delay amount is set depending on a cycle of the clock.