Resistive memory with varying dopant concentration in select transistor channel
A nonvolatile semiconductor memory device according to one embodiment includes: a first wiring extending in a first direction as a longitudinal direction thereof; a second wiring extending in a second direction as a longitudinal direction thereof, the second direction intersecting with the first direction; a memory cell disposed at an intersection portion of the first wiring and the second wiring, the memory cell including a variable resistive element; a select transistor having one end connected to the second wiring; and a third wiring connected to the other end of the select transistor. A semiconductor layer included in the select transistor has a first impurity concentration at the second end. An impurity concentration of the semiconductor layer decrease to a second impurity concentration from the first impurity concentration as approaching to the first end from the second end.
1. A semiconductor memory device, comprising:
a first wiring extending in a first direction as a longitudinal direction thereof;
a second wiring extending in a second direction as a longitudinal direction thereof, the second direction intersecting with the first direction;
a memory cell disposed at an intersection portion of the first wiring and the second wiring, the memory cell including a variable resistive element;
a select transistor having one end connected to the second wiring; and
a third wiring connected to the other end of the select transistor,
the select transistor including:
a semiconductor layer including impurities therein, the semiconductor layer having a first end connected to the second wiring and a second end connected to the third wiring;
a gate insulating film disposed on a side surface of the semiconductor layer; and
a select gate line facing the semiconductor layer via the gate insulating film,
the semiconductor layer having a first impurity concentration at the second end,
an impurity concentration of the semiconductor layer decreasing to a second impurity concentration from the first impurity concentration as approaching to the first end from the second end, and
an impurity concentration ρ of the semiconductor layer at a position that is away from the second end of the semiconductor layer by a distance Z is
ρ
=
max
[
ρ
o
·
exp
(
-
log
(
ρ
o
N
BG
)
2
(
Z
-
Zo
)
2
x
j
2
)
,
N
BG
]
,
where ρo is an impurity concentration of the second end, Zo is coordinates of the second end, x j is an attenuation constant, and N BG is an impurity concentration after attenuation of the semiconductor layer.
2. The semiconductor memory device according to claim 1 , wherein the second impurity concentration is one hundredth or less of the first impurity concentration.
3. The semiconductor memory device according to claim 1 , wherein the first impurity concentration is 5×10 19 [cm −3 ] or more.