Fabrication method of a stack of electronic devices

1. A fabrication method of a stack of electronic devices, comprising the following steps:

a) providing a first structure successively comprising a first substrate, a first electronic device, a first dielectric layer, and a first semiconductor layer;

b) providing a second structure successively comprising a second substrate, an active layer, a second dielectric layer, and a second semiconductor layer, the active layer being designed to form a second electronic device;

c) bonding the first and second structures by direct bonding between the first and second semiconductor layers so as to form a bonding interface;

d) removing the second substrate of the second structure so as to expose the active layer;

e) introducing dopants into the first and second semiconductor layers so as to form a ground plane.

2. Method according to claim 1 , wherein the first and/or second semiconductor layers comprise an amorphous film before step c), and wherein the method comprises a crystallization step of the amorphous film or films so that a crystallization front propagates at the bonding interface.

3. Method according to claim 2 , wherein the amorphous films of the first and second semiconductor layers present different thicknesses so that the crystallization front propagates through the bonding interface.

4. Method according to claim 2 , wherein the first and second semiconductor layers present different crystallization rates so that the crystallization front propagates through the bonding interface.

5. Method according to claim 3 , wherein the first and second semiconductor layers present different crystallization rates so that the crystallization front propagates through the bonding interface (IC).

6. Method according to claim 2 , wherein the first semiconductor layer comprises a polycrystalline seed covered by an amorphous film before step c), and in that the second semiconductor layer is totally amorphous before step c).

7. Method according to claim 3 , wherein the first semiconductor layer comprises a polycrystalline seed covered by an amorphous film before step c), and in that the second semiconductor layer is totally amorphous before step c).

8. Method according to claim 4 , wherein the first semiconductor layer comprises a polycrystalline seed covered by an amorphous film before step c), and in that the second semiconductor layer is totally amorphous before step c).

9. Method according to claims 2 , wherein the crystallization step is executed by a suitable thermal annealing to simultaneously thermally activate the dopants introduced in step e).

10. Method according to claim 1 , wherein the first and/or second semiconductor layers comprise a surface covered by an oxide film before step c), and wherein the method comprises a surface treatment step consisting in removing the oxide film from the surface of the first and/or second semiconductor layers before step c) so as to obtain hydrophobic bonding in step c).

11. Method according to claim 1 , comprising a surface activation step consisting in bombarding the surface of the first and second semiconductor layers before step c) by a beam of species.

12. Method according to claim 1 , comprising a planarization step of the first and second semiconductor layers before step c) so as to obtain a surface roughness of less than 2.5 Å RMS.

13. Method according to claim 1 , wherein the first and second semiconductor layers are made from a material selected from the group comprising Si, Ge, and Si—Ge.

14. Method according to claim 1 , wherein step e) is executed by introducing dopants through the exposed active layer.