IP Library Granted Patent US 9,825,597
Granted Patent B2
US 9,825,597 · App. 15/389,097 · Granted Nov 21, 2017

Impedance transformation circuit for amplifier

Inventor: Leslie Paul Wallis (Ottawa, CA)
Assignee: Skyworks Solutions, Inc.
H03F1/565H03F1/223H03F1/342H03F3/195H03F3/213H04B1/1607H03F2200/18H03F2200/294H03F2200/387H03F2200/451H03F2200/75
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,825,597
App. No.
15/389,097
Granted
Nov 21, 2017
Kind
B2
Abstract

Aspects of this disclosure relate to an impedance transformation circuit for use in an amplifier, such as a low noise amplifier. The impedance transformation circuit includes a matching circuit including a first inductor. The impedance transformation circuit also includes a second inductor. The first and second inductors are magnetically coupled to each other to provide negative feedback to linearize the amplifier.

Claims (31)

1. A low noise amplifier comprising:

a matching circuit including a first inductor, a series inductor having a first end configured to receive a radio frequency signal and a second end electrically coupled to the first inductor, and a shunt capacitor electrically coupled to the first end of the series inductor;

an amplification circuit configured to receive the radio frequency signal by way of the first inductor and to amplify the radio frequency signal; and

a second inductor, the first and second inductors magnetically coupled to each other to provide negative feedback to linearize the low noise amplifier.

2. The low noise amplifier of claim 1 wherein the amplification circuit includes a common source amplifier and the second inductor is a source degeneration inductor.

3. The low noise amplifier of claim 2 wherein the amplification circuit further includes a cascode transistor in series with the common source amplifier.

4. The low noise amplifier of claim 1 wherein the amplification circuit includes a common emitter amplifier and the second inductor is an emitter degeneration inductor.

5. The low noise amplifier of claim 4 wherein the amplification circuit further includes a cascode transistor in series with the common emitter amplifier.

6. The low noise amplifier of claim 1 wherein the first inductor, the second inductor, and the amplification circuit of amplifier are embodied on a single die.

7. A low noise amplifier comprising:

a matching circuit including a first inductor, a series inductor having a first end configured to receive a radio frequency signal and a second end electrically coupled to the first inductor, and a direct current blocking capacitor configured to provide the radio frequency signal to the series inductor;

an amplification circuit configured to receive the radio frequency signal by way of the first inductor and to amplify the radio frequency signal; and

a second inductor, the first and second inductors magnetically coupled to each other to provide negative feedback to linearize the low noise amplifier.

8. The low noise amplifier of claim 7 wherein the matching circuit further includes a shunt capacitor electrically coupled to the first end of the series inductor.

9. An impedance transformation circuit for use in an amplifier, the impedance transformation circuit comprising:

a matching circuit including a first inductor a series inductor having a first end configured to receive a radio frequency signal and a second end electrically coupled to the first inductor, and at least one of a shunt capacitor electrically coupled to the first end of the series inductor or a direct current blocking capacitor configured to provide the radio frequency signal to the series inductor; and

a second inductor, the first and second inductors magnetically coupled to each other to provide negative feedback to linearize the amplifier.

10. The impedance transformation circuit of claim 9 wherein the second inductor is configured as a source degeneration inductor.

11. The impedance transformation circuit of claim 9 wherein the second inductor is configured as an emitter degeneration inductor.

12. The impedance transformation circuit of claim 9 wherein the first inductor is configured to provide the radio frequency signal to an amplification circuit of the amplifier.

13. A front end system comprising:

a low noise amplifier including (i) a matching circuit including a first inductor, a series inductor having a first end configured to receive a radio frequency signal and a second end electrically coupled to the first inductor, and at least one of a shunt capacitor electrically coupled to the first end of the series inductor or a direct current blocking capacitor configured to provide the radio frequency signal to the series inductor; (ii) an amplification circuit configured to receive the radio frequency signal by way of the first inductor and to amplify the radio frequency signal; and (iii) a second inductor magnetically coupled with the first inductor to provide negative feedback to linearize the low noise amplifier; and

a bypass path.

14. The front end system of claim 13 further comprising a multi-throw switch having at least a first throw electrically connected to the low noise amplifier and a second throw electrically connected to the bypass path.

15. The front end system of claim 14 further comprising a power amplifier, the multi-throw switch having a third throw electrically coupled to the power amplifier.

16. The front end system of claim 14 further comprising a second multi-throw switch having at least a first throw electrically connected to the low noise amplifier and a second throw electrically connected to the bypass path, the low noise amplifier being included in a first signal path between the multi-throw switch and the second multi-throw switch, and the bypass path being included in a second signal path between the multi-throw switch and the second multi-throw switch.

17. The front end system of claim 14 wherein the multi-throw switch is configured to electrically connect an input of the low noise amplifier to an antenna port in a first state, and the multi-throw switch is configured to electrically connect the bypass path to the antenna port in a second state.

18. The front end system of claim 13 wherein the amplification circuit includes a cascode transistor in series with either a common source amplifier or a common emitter amplifier.

19. The front end system of claim 13 wherein the matching circuit includes the shunt capacitor.

20. The front end system of claim 13 wherein the matching circuit includes the direct current blocking capacitor.

21. The front end system of claim 13 wherein the matching circuit includes the shunt capacitor and the direct current blocking capacitor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 10, 2017
From: WALLIS, LESLIE PAUL
To: SKYWORKS SOLUTIONS, INC.
Reel/Frame 042328/0524 →
Continuity (2)
Provisional Application 62273225 · Dec 30, 2015
Related Publication 20170194918A1 · Jul 6, 2017