Adaptive equalization using correlation of edge samples with data patterns
An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.
1. A receiver comprising:
an equalizer to issue an equalized data signal responsive to an input data signal;
a data sampler to sample the equalized data signal on edges of a data-clock signal, thereby generating a series of data samples;
an edge sampler to sample at least one of the input data signal and the equalized data signal on edges of an edge-clock signal, thereby generating a series of edge samples; and
equalizer control circuitry to receive the series of data samples and the series of edge samples, the equalizer control circuitry including:
a pattern detector to detect a pattern from the series of data samples, the pattern including successive first bit values followed by a transition to a second bit value;
a phase detector to generate a relative-timing signal responsive to the series of data samples and the series of edge samples; and
equalization circuitry to adjust the equalizer responsive to the relative-timing signal and the detected pattern of the series of data samples.
2. The receiver of claim 1 , further comprising a second data sampler to sample the equalized data signal, thereby generating a second series of data samples.
3. The receiver of claim 2 , further comprising a second edge sampler to sample at least one of the input data signal and the equalized data signal on edges of a second edge-clock signal, thereby generating a second series of edge samples.
4. The receiver of claim 2 , the pattern detector to detect the pattern from the series of data samples and the second series of data samples.
5. The receiver of claim 2 , further comprising a multiplexer to convey the first-mentioned series of data samples and the second series of data samples to the equalizer control circuitry.
6. The receiver of claim 5 , wherein the multiplexer deserializes the first-mentioned series of data samples and the second series of data samples.
7. The receiver of claim 1 , further comprising clock-recovery circuitry to recover the data-clock signal responsive to the series of data samples.
8. The receiver of claim 1 , the equalizer control circuitry including memory to store the pattern.
9. The receiver of claim 8 , the memory to store the pattern and at least one additional pattern, the equalizer control circuitry to adjust the equalizer responsive to the pattern and the at least one additional pattern.
10. A method of receiving an input data signal, the method comprising:
equalizing the input data signal to create an equalized signal;
sampling the equalized signal to generate a series of data samples, each data sample representing one of a first value and a second value;
sampling at least one of the input data signal and the equalized signal to generate a series of edge samples;
comparing the data samples with the edge samples to produce a relative-timing signal;
adjusting data-sampling timing responsive to the data samples and the edge samples; and
adjusting the equalizing responsive to a specific pattern of the data samples, the specific pattern including successive bits of the first value followed by a transition to a bit of the second value.
11. The method of claim 10 , further comprising receiving and loading the specific pattern.
12. The method of claim 10 , further comprising adjusting the equalizing responsive to a second specific pattern of the data samples.
13. The method of claim 10 , further comprising sampling the equalized signal to generate a second series of data samples, each data sample of the second series of data samples representing one of a first value and a second value.
14. The method of claim 13 , wherein the specific pattern includes the data samples from the second series of data samples.
15. The method of claim 10 , wherein the specific pattern includes a second transition to the first value exactly one bit after the transition to the bit of the second value.
16. A receiver comprising:
an equalizer to issue an equalized data signal responsive to an input data signal;
a data sampler to sample the equalized data signal, thereby generating data samples;
an edge sampler to sample at least one of the input data signal and the equalized data signal, thereby generating edge samples; and
equalizer control means for receiving the data samples and the edge samples, the equalizer control means including a phase detector to generate a relative-timing signal responsive to the data samples and the edge samples, the equalizer control means to adjust the equalizer responsive to the relative-timing signal and a specific pattern of the data samples, the specific pattern including successive first bit values followed by a transition to a second bit value.
17. The receiver of claim 16 , further comprising memory to load with the specific pattern.
18. The receiver of claim 17 , the memory to store the specific pattern and at least one additional pattern, the equalizer control means to adjust the equalizer responsive to the specific pattern and the at least one additional pattern.
19. The receiver of claim 16 , further comprising means for recovering first and second clock signals from at least one of the input data signal and the equalized data signal, the data sampler and the edge sampler to sample the input data signal respectively timed to the first clock signal and the second clock signal.
20. The receiver of claim 16 , further comprising a second data sampler to sample the equalized data signal, thereby generating second data samples, wherein the specific pattern includes at least one of the second data samples.