Nonvolatile semiconductor memory device

1. A nonvolatile semiconductor memory device, comprising:

a cell array including a plurality of unit cell arrays arranged in a matrix, one of the unit cell arrays including a plurality of bit lines, a plurality of word lines intersecting the bit lines, and a plurality of electrically rewritable memory cells connected at intersections of the bit lines and the word lines between both lines and each including a variable resistance element; and

a control circuit corresponding to one of the unit cell arrays configured to control voltages applied to the bit lines and the word lines, the control circuit including a row control circuit to select the word lines, and a column control circuit to select the bit lines, at least a part of the control circuit being provided beneath the corresponding unit cell array,

the control circuit, during data write to the cell array, simultaneously writing a part of data having a plurality of bits to at least one of the memory cells belonging to one of the unit cell arrays, and another part of the data to at least one of the memory cells belonging another of the unit cell arrays, the memory cells written simultaneously being physically separated apart more than one memory cell from each other.

2. The nonvolatile semiconductor memory device according to claim 1 , wherein at least a part of the row control circuit is provided beneath the corresponding unit cell array.

3. The nonvolatile semiconductor memory device according to claim 1 , wherein at least a part of the column control circuit is provided beneath the corresponding unit cell array.

4. The nonvolatile semiconductor memory device according to claim 1 , further comprising

a first circuit configured to apply voltages to the word lines selected by the row control circuit, and apply voltages to the bit lines selected by the column control circuit, and

at least a part of the first circuit is provided beneath the corresponding unit cell array.

5. The nonvolatile semiconductor memory device according to claim 1 , wherein the variable resistance element includes a chalcogenide compound.

6. The nonvolatile semiconductor memory device according to claim 1 , wherein the nonvolatile semiconductor memory device is a phase change random access memory.

7. The nonvolatile semiconductor memory device according to claim 1 , wherein

each of the memory cells has a physical address assigned to each of unit cell arrays, and

the memory cells written simultaneously have the same physical address.

8. The nonvolatile semiconductor memory device according to claim 1 , wherein the column control circuit includes a sense amplifier circuit configured to sense one of the selected bit lines.

9. The nonvolatile semiconductor memory device according to claim 1 , wherein the column control circuit includes a plurality of sense amplifier circuits configured to sense the selected bit lines.

10. The nonvolatile semiconductor memory device according to claim 1 , wherein the row control circuit includes a latch circuit configured to store whether the corresponding unit cell array is failed or not.

11. The nonvolatile semiconductor memory device according to claim 1 , further comprising a global word line and a local address line, wherein

the row control circuits are configured to control the global word line and the local address line, and

the column control circuits and the row control circuits are configured to select the plurality of unit cell arrays simultaneously.

12. The nonvolatile semiconductor memory device according to claim 1 , further comprising a plurality of IO pads, each of the IO pads being provided to a certain number of the unit cell arrays and configured to execute data input/output to/from the unit cell arrays via the column control circuits.

13. The nonvolatile semiconductor memory device according to claim 12 , wherein the IO pads, when inputting Nd-bit data, Nd=an integer of 2 or more, are configured to transfer the Nd-bit data to Nd column control circuits one bit at a time.

14. The nonvolatile semiconductor memory device according to claim 13 , wherein each of the Nd column control circuits is configured to access one memory cell of the corresponding unit cell array.

15. The nonvolatile semiconductor memory device according to claim 1 , wherein each of the memory cells includes a first element configured to control a current flow.

16. A nonvolatile semiconductor memory device, comprising:

a cell array including a plurality of unit cell arrays arranged in a matrix, one of the unit cell arrays including a plurality of bit lines, a plurality of word lines intersecting the bit lines, and a plurality of electrically rewritable memory cells connected at intersections of the bit lines and the word lines between both lines; and

a control circuit corresponding to one of the unit cell arrays configured to control voltages applied to the bit lines and the word lines, the control circuit including a row control circuit to select the word lines, and a column control circuit to select the bit lines, at least a part of the control circuit being provided beneath the corresponding unit cell array,

each of the memory cells including a variable resistance element and a first element connected to the variable resistance element in series, the variable resistance element including a chalcogenide compound, the first element being configured to control a current flow,

the control circuit, during data write to the cell array, simultaneously writing a part of data having a plurality of bits to at least one of the memory cells belonging to one of the unit cell arrays, and another part of the data to at least one of the memory cells belonging another of the unit cell arrays, the memory cells written simultaneously being physically separated apart more than one memory cell from each other, and

the nonvolatile semiconductor memory device being a phase change random access memory.