Efficient data access control device for neural network hardware acceleration system

1. A data access control device used for a neural network acceleration system, comprising:

a parameter access control circuit, configured to read parameters required by a plurality of processing elements (PEs) from a memory, and perform bit-width transformation operation on said parameters and output the transformed parameters to said PEs;

a vector access control circuit, configured to read vectors required by PEs from the memory, perform bit-width transformation operation on said vectors and output the transformed vectors to said PEs; and

a computation result access control circuit, configured to read computation results from said PEs, perform bit-width transformation operation on said computation results and output the transformed computation results to the memory,

wherein the bit-width transformation operation on data comprises, if the data is the parameters or the vectors, splitting data into a plurality of smaller bit width data, and

wherein the bit-width transformation operation on data comprises, if the data is the computation results, assembling a plurality of small bit-width data into a single large bit-width data.

2. The device of claim 1 , wherein said parameter access control circuit further comprises:

at least one parameter buffer, configured to store received parameters; and

at least one bit-width converter, configured to perform bit-width transformation operation on said parameters.

3. The device of claim 1 , wherein said vector access control circuit further comprises:

at least one vector buffer, configured to store received vectors; and

at least one bit-width converter, configured to perform bit-width transformation operation on said vectors.

4. The device of claim 1 , wherein said computation result access control circuit further comprises:

at least one result buffer, configured to store received computation results; and

at least one bit-width converter, configured to perform bit-width transformation operation on said computation results.

5. The device of any of claims 2 - 4 , wherein the number of bit-width converters is no less than m×n÷d, wherein m is the number of said PEs, n is the number of data to be processed or to be output by one PE per computation cycle, and d is the computation delay.

6. The device of any of claims 2 - 4 , wherein said bit-width converter operation is implemented by two cascaded asynchronous FIFOs, one is a 512 bit-to-64 bit converter and the other is 64 bit-to-16 bit converter.

7. The device of claim 1 , wherein said parameters comprises at least weight, bias, diagonal matrix data of said neural network.

8. The data access control device of claim 1 ,

wherein the parameter access control circuit is configured to output the transformed parameters to each PE of said PEs,

wherein the vector access control circuit is configured to output the transformed vectors to each PE of said PEs, and

wherein the computation result access control circuit is configured to read computation results from each PE of said PEs.

9. The data access control device of claim 8 ,

wherein the parameter access control circuit is not a part of said PEs, and

wherein the vector access control circuit is not a part of said PEs.

10. The data access control device of claim 1 ,

wherein the parameter access control circuit is not a part of said PEs, and

wherein the vector access control circuit is not a part of said PEs.

11. A data access control device used for a neural network acceleration system, comprising:

first memory configured for storing weight data of the neural network;

second memory configured for storing input vectors, bias data of the neural network;

first memory controller configured for reading the weight data from the first memory into the first memory controller and outputting said weight data from the first memory controller to a plurality of processing elements (PEs);

second memory controller configured for reading the input vectors and bias data from the second memory into the second memory controller, conducting bit-width transformation operation on the input vectors and bias data, and outputting said transformed input vectors and bias data from the second memory controller to the processing elements.

12. The data access control device of claim 11 , wherein the second memory controller further comprising:

at least one bit-width converter, configured to perform bit-width transformation operation.

13. The device of claim 12 , wherein said bit-width converter operation is implemented by two cascaded asynchronous FIFOs, one is a 512 bit-to-64 bit converter and the other is 64 bit-to-16 bit converter.

14. The device of claim 12 , wherein the number of bit-width converters is no less than m×n÷d, wherein m is the number of said PEs, n is the number of data to be processed or to be output by one PE per computation cycle, and d is the computation delay.

15. The device of claim 11 , wherein the second memory controller further comprising:

a computation result access control circuit, configured to read computation results from said PEs, perform bit-width transformation operation on said computation results and output the transformed computation results to the first memory.

16. The data access control device of claim 15 , wherein the bit-width transformation operation on data comprises, if the data is the computation results, assembling a plurality of small bit-width data into a single large bit-width data.

17. The data access control device of claim 11 , wherein the bit-width transformation operation on data comprises, if the data is the input vectors or the bias data, splitting data into a plurality of smaller bit width data.