IP Library › Granted Patent US 9,971,373
Granted Patent B1
US 9,971,373 · App. 15/391,966 · Granted May 15, 2018

Reference voltage generator

Inventor: Teh-Shang Lu (Sunnyvale, CA)
Assignee: AUCMOS Technologies USA, Inc.
G05F3/24H03H7/0138
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Quick Facts
Patent No.
US 9,971,373
App. No.
15/391,966
Granted
May 15, 2018
Kind
B1
Abstract

A reference voltage generation circuit includes (a) a native MOS transistor coupled to between a power supply voltage source, and the output terminal of the reference voltage generation circuit; (b) an enhancement mode MOS transistor coupled between the output terminal and ground; and (c) a filter circuit that are coupled to the gate terminals of both the native MOS transistor, the enhancement mode transistor and the output terminal of the reference voltage generation circuit, in which the filter circuit has a transfer function including one or more zeroes at predetermined noise frequencies.

Claims (8)

1. A reference voltage generation circuit connected between a power supply voltage source and ground, providing a reference voltage at an output terminal, comprising:

a native MOS transistor having a gate terminal, a source terminal and a drain terminal, the drain terminal being coupled to the power supply voltage source, and the source terminal being coupled to the output terminal to provide the reference voltage;

an enhancement mode MOS transistor having a gate terminal, a drain terminal and a source terminal, the drain terminal being coupled to the output terminal, and the source terminal being coupled to ground; and

a filter circuit coupled to the gate terminal of the native MOS transistor, the gate terminal of the enhancement mode transistor and the output terminal, the filter circuit having a transfer function including one or more zeroes.

2. The reference voltage generation circuit of claim 1 , wherein the filter circuit comprises two or more of: resistors, capacitors and inductors.

3. The reference voltage generation circuit of claim 1 , wherein the drain terminal of the native MOS transistor is coupled to the power supply voltage source by one or more diode-connected additional MOS native transistor that are connected in series.

4. The reference voltage generation circuit of claim 3 , further comprising a switch circuit which, when conducting, allows a current to flow between the power supply voltage source and the additional native MOS transistors.

5. The reference voltage generation circuit of claim 1 , wherein one of the zeroes is provided at 217 Hz.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2018
From: AUCMOS TECHNOLOGIES USA, INC.
To: CORE CHIP TECHNOLOGY (NANJING) CO., LTD.
Reel/Frame 046821/0597 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2018
From: LU, TEH-SHANG
To: AUCMOS TECHNOLOGIES USA, INC.
Reel/Frame 045498/0551 →