Low-jitter phase-locked loop circuit
A phase-locked loop circuit includes (a) a phase frequency detector which receives the input signal of the phase-locked loop and a feedback signal that is derived from the output signal of the phase-locked loop, the phase-frequency detector providing a phase-difference signal indicating a difference in phase or frequency between the input signal and the feedback signal; (b) a voltage control oscillator which receives a voltage control signal and which provide the output signal of the phase-locked loop according to the voltage control signal; (c) first and second charge pump-filter circuits each receiving the phase difference signal and each comprising: (i) a charge pump circuit which provide a predetermined signal in accordance with the phase difference signal; and (ii) a filter circuit receiving the predetermined signal to provide a filtered signal, the filter circuit comprising one or more resistors and one or more capacitors; and (d) a summing circuit which sums the filtered signal of the first charge pump-filter circuit and the filtered signal of the second charge pump-filter circuit to provide the voltage control signal.
1. A phase-locked loop circuit receiving an input signal and an output signal, comprising:
a phase frequency detector which receives the input signal and a feedback signal, the feedback signal being derived from the output signal of the phase-locked loop, and which provides a phase-difference signal indicating a difference in phase or frequency between the input signal and the feedback signal;
a voltage controlled oscillator which receives a control signal and which provide the output signal of the phase-locked loop according to the control signal;
first and second charge pump-filter circuits each receiving the phase difference signal and each comprising:
a charge pump circuit which provide a predetermined signal in accordance with the phase difference signal; and
a filter circuit receiving the predetermined signal to provide a filtered signal, the filter circuit comprising one or more resistors and one or more capacitors; and
a summing circuit which sums the filtered signal of the first charge pump-filter circuit and the filtered signal of the second charge pump-filter circuit to provide the control signal, wherein the first and second charge-pump-filter circuits and the summing circuit together implement a transfer function that has at least a zero of:
H
(
s
)
=
(
1
+
sR
1
C
1
)
(
s
2
C
2
C
3
+
sC
1
)
(
1
+
sR
2
C
3
)
in which R 1 , R 2 , C1, C 2 and C 3 are values of resistors and capacitors in the first and second charge-pump-filter circuits.
2. The phase-locked loop circuit of claim 1 , wherein the charge pump circuit in each of the charge pump-filter circuits comprises a first current source providing a first predetermined current from a power supply voltage source and a second current source sinking a second predetermined current to a ground voltage.
3. The phase-locked loop circuit of claim 1 , wherein the first and second charge-pump-filter circuit and the summing circuit together implement the transfer function of a conventional charge pump circuit and a conventional loop filter circuit.
4. The phase-locked loop of claim 1 , wherein the summing circuit comprises a voltage mode summing circuit.
5. The phase-locked loop of claim 1 , wherein the summing circuit comprises a current mode summing circuit.