Optimal write method for a ferroelectric memory
A method for programming a memory cell to a predetermined programmed state includesL (a) preparing the memory cell for a write operation; (b) sending a train of programming pulses, each programming pulse being a pulse having a magnitude sufficient to program the memory cell to the predetermined programmed state; (c) preparing the memory cell for a read operation; and (d) reading the programmed state of the memory cell to ascertain whether or not the predetermined programmed state is in the memory cell. In one embodiment, the method repeats steps (a)-(d), when the programmed state of the memory cell is not the predetermined programmed state. In one embodiment, the number of times steps (a)-(d) is repeated is determined based on both a probability of successfully writing the memory cell using a single write pulse and a probability of chaotic switching.
1. A method for programming a memory cell to a predetermined programmed state, comprises:
(a) preparing the memory cell for an initial access write operation, wherein the preparing for the initial access write operation includes a write setup step;
(b) sending a train of contiguous programming pulses during the initial access write operation, each programming pulse having a magnitude sufficient to program the memory cell to the predetermined programmed state;
(c) preparing the memory cell for a read operation;
(d) reading the programmed state of the memory cell to ascertain whether or not the predetermined programmed state is in the memory cell.
2. The method of claim 1 , wherein steps (e) is carried out up to a predetermined number of times.
3. The method of claim 2 , further comprising determining the predetermined number of times based on a probability of successfully writing the memory cell using a single write pulse.
4. The method of claim 2 , further comprising determining the predetermined number of times based on both a probability of successfully writing the memory cell using a single write pulse and a probability of chaotic switching per write pulse.
5. The method of claim 1 , wherein the memory cell comprises a ferroelectric memory element.
6. The method of claim 1 , wherein the number of programming pulses in the train of programming pulses is selected to achieve a target probability of successful write of the memory cell within a target write latency.