IP Library › Granted Patent US 10,542,333
Granted Patent B2
US 10,542,333 · App. 15/396,028 · Granted Jan 21, 2020

Technologies for a low-latency interface to data storage

Inventor: Steven C. Miller (Livermore, CA)
Assignee: Intel Corporation
H04Q11/0005B25J15/0014B65G1/0492G02B6/3882G02B6/3893G02B6/3897G02B6/4292G02B6/4452G05D23/1921G05D23/2039G06F1/183G06F3/061G06F3/064G06F3/067G06F3/0611G06F3/0613G06F3/0616G06F3/0619G06F3/0625G06F3/0631G06F3/0638G06F3/0647G06F3/0653G06F3/0655G06F3/0658G06F3/0659G06F3/0664G06F3/0665G06F3/0673G06F3/0679G06F3/0683G06F3/0688G06F3/0689G06F8/65G06F9/30036G06F9/3887G06F9/4401G06F9/505G06F9/5016G06F9/5044G06F9/5072G06F9/5077G06F9/544G06F11/141G06F11/3414G06F12/0862G06F12/0893G06F12/10G06F12/109G06F12/1408G06F13/161G06F13/1668G06F13/1694G06F13/409G06F13/4022G06F13/4068G06F13/42G06F13/4282G06F15/8061G06F16/9014G06Q10/06G06Q10/06314G07C5/008G08C17/02G11C5/02G11C5/06G11C7/1072G11C11/56G11C14/0009H03M7/30H03M7/3084H03M7/3086H03M7/4031H03M7/4056H03M7/4081H03M7/6005H03M7/6023H04B10/2504H04L9/0643H04L9/14H04L9/3247H04L9/3263H04L12/2809H04L29/12009H04L41/024H04L41/046H04L41/082H04L41/0813H04L41/0896H04L41/145H04L41/147H04L43/08H04L43/0817H04L43/0876H04L43/0894H04L43/16H04L45/02H04L45/52H04L47/24H04L47/38H04L47/765H04L47/782H04L47/805H04L47/82H04L47/823H04L49/00H04L49/15H04L49/25H04L49/357H04L49/45H04L49/555H04L67/02H04L67/10H04L67/1004H04L67/1008H04L67/1012H04L67/1014H04L67/1029H04L67/1034H04L67/1097H04L67/12H04L67/16H04L67/306H04L67/34H04L69/04H04L69/329H04Q1/04H04Q11/00H04Q11/0003H04Q11/0062H04Q11/0071H04W4/023H05K1/0203H05K1/181H05K5/0204H05K7/1418H05K7/1421H05K7/1422H05K7/1442H05K7/1447H05K7/1461H05K7/1487H05K7/1489H05K7/1491H05K7/1492H05K7/1498H05K7/2039H05K7/20709H05K7/20727H05K7/20736H05K7/20745H05K7/20836H05K13/0486G06F2209/5019G06F2209/5022G06F2212/1008G06F2212/1024G06F2212/1041G06F2212/1044G06F2212/152G06F2212/202G06F2212/401G06F2212/402G06F2212/7207G06Q10/087G06Q10/20G06Q50/04G08C2200/00H04B10/25H04L41/12H04L41/5019H04L43/065H04Q2011/0037H04Q2011/0041H04Q2011/0052H04Q2011/0073H04Q2011/0079H04Q2011/0086H04Q2213/13523H04Q2213/13527H04W4/80H05K7/1485H05K2201/066H05K2201/10121H05K2201/10159H05K2201/10189Y02D10/14Y02D10/151Y02P90/30Y04S10/54Y10S901/01
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Quick Facts
Patent No.
US 10,542,333
App. No.
15/396,028
Filed
Dec 30, 2016
Granted
Jan 21, 2020
Kind
B2
Art Unit
2181
USPC
710/107
Abstract

Technologies for a low-latency interface with data storage of a storage sled in a data center are disclosed. In the illustrative embodiment, a storage sled stores metadata including the location of data in a storage device in low-latency non-volatile memory. When accessing data, the storage sled may access the metadata on the low-latency non-volatile memory and then, based on the location determined by the access to the metadata, access the location of the data in the storage device. Such an approach results in only one access to the data storage in order to read the data instead of two.

Claims (49)

1. A storage sled for a low-latency interface to data storage of the storage sled in a data center, the storage sled comprising:

a communication engine to:

receive, from a compute sled of the data center, durable data to be stored on the storage sled;

send, to another storage sled, the durable data; and

receive, from the other storage sled, an acknowledgement of receipt of the durable data;

a storage controller to:

store the durable data in a low-latency non-volatile memory of the storage sled; and

store the durable data in the data storage,

wherein the communication engine is further to send, to the compute sled and in response to (i) storage of the durable data in the low-latency non-volatile memory and (ii) receipt of the acknowledgement of receipt of the durable data by the other storage sled, confirmation of receipt of the durable data prior to storage of the durable data in the data storage, and

wherein a latency of a storage of the durable data in the low-latency non-volatile memory is less than a latency of a storage of the durable data in the data storage.

2. The storage sled of claim 1 , wherein to store the durable data in the low-latency non-volatile memory comprises to encrypt, by the low-latency non-volatile memory, the durable data in the low-latency non-volatile memory with a non-volatile encryption key, and wherein to store the durable data in the data storage comprises to decrypt, by the low-latency non-volatile memory, the durable data.

3. The storage sled of claim 1 , wherein the data storage comprises NAND flash memory and wherein to store the durable data in the data storage comprises to store the durable data in the NAND flash memory.

4. The storage sled of claim 3 , wherein the low-latency non-volatile memory is a byte-addressable write-in-place memory.

5. The storage sled of claim 4 , wherein the byte-addressable write-in-place memory comprises at least one of a chalcogenide phase change material, a 3-dimensional cross point memory, a ferroelectric transistor random-access memory, a nanowire-based non-volatile memory, a phase change memory, a memory that incorporates memristor technology, a magnetoresistive random-access memory (MRAM), and a spin torque transfer MRAM.

6. The storage sled of claim 1 , wherein the latency for a storage of the durable data in the data storage is at least ten times the latency for a storage of the durable data in the low-latency non-volatile memory.

7. The storage sled of claim 1 , wherein the data storage comprises byte-addressable, write-in-place non-volatile memory and wherein to store the durable data in the data storage comprises to store the durable data in the byte-addressable, write-in-place non-volatile memory.

8. The storage sled of claim 1 , wherein the data storage comprises a plurality of storage devices in a storage cage and wherein the low-latency non-volatile memory is not in the storage cage.

9. The storage sled of claim 1 , wherein the low-latency non-volatile memory is in a dual in-line memory module (DIMM) package.

10. One or more non-transitory computer-readable media comprising a plurality of instructions stored thereon that, when executed, causes a storage sled to:

receive, from a compute sled of a data center, durable data to be stored on the storage sled;

store the durable data in a low-latency non-volatile memory of the storage sled;

store the durable data in data storage of the storage sled;

send, to another storage sled, the durable data; and

receive, from the other storage sled, an acknowledgement of receipt of the durable data; and

send, to the compute sled and in response to storage of the durable data in the low-latency non-volatile memory, confirmation of receipt of the durable data prior to storage of the durable data in the data storage and after receipt of the acknowledgement of receipt of the durable data by the other storage sled, and

wherein a latency of a storage of the durable data in the low-latency non-volatile memory is less than a latency of a storage of the durable data in the data storage.

11. The one or more non-transitory computer-readable media of claim 10 , wherein to store the durable data in the low-latency non-volatile memory comprises to encrypt, by the low-latency non-volatile memory, the durable data in the low-latency non-volatile memory with a non-volatile encryption key, and wherein to store the durable data in the data storage comprises to decrypt, by the low-latency non-volatile memory, the durable data.

12. The one or more non-transitory computer-readable media of claim 10 , wherein the data storage comprises NAND flash memory and wherein to store the durable data in the data storage comprises to store the durable data in the NAND flash memory.

13. The one or more non-transitory computer-readable media of claim 10 , wherein the latency for a storage of the durable data in the data storage is at least ten times the latency for a storage of the durable data in the low-latency non-volatile memory.

14. The one or more non-transitory computer-readable media of claim 13 , wherein the low-latency non-volatile memory is a byte-addressable write-in-place memory.

15. The one or more non-transitory computer-readable media of claim 10 , wherein the byte-addressable write-in-place memory comprises at least one of a chalcogenide phase change material, a 3-dimensional cross point memory, a ferroelectric transistor random-access memory, a nanowire-based non-volatile memory, a phase change memory, a memory that incorporates memristor technology, a magnetoresistive random-access memory (MRAM), and a spin torque transfer MRAM.

16. The one or more non-transitory computer-readable media of claim 10 , wherein the data storage comprises byte-addressable, write-in-place non-volatile memory and wherein storing the durable data in the data storage comprises storing the durable data in the byte-addressable, write-in-place non-volatile memory.

17. The one or more non-transitory computer-readable media of claim 10 , wherein the data storage comprises a plurality of storage devices in a storage cage and wherein the low-latency non-volatile memory is not in the storage cage.

18. The one or more non-transitory computer-readable media of claim 10 , wherein the low-latency non-volatile memory is in a dual in-line memory module (DIMM) package.

19. A method for a low-latency interface to data storage of a storage sled in a data center, the method comprising:

receiving, by the storage sled and from a compute sled of the data center, durable data to be stored on the storage sled;

sending, by the storage sled and to another storage sled, the durable data;

receiving, by the storage sled and from the other storage sled, an acknowledgement of receipt of the durable data;

storing, by the storage sled, the durable data in a low-latency non-volatile memory of the storage sled;

storing, by the storage sled, the durable data in the data storage; and

sending, by the storage sled and to the compute sled and in response to (i) storage of the durable data in the low-latency non-volatile memory and (ii) receipt of the acknowledgement of receipt of the durable data by the other storage sled, confirmation of receipt of the durable data prior to storage of the durable data in the data storage,

wherein a latency of a storage of the durable data in the low-latency non-volatile memory is less than a latency of a storage of the durable data in the data storage.

20. The method of claim 19 , wherein storing the durable data in the low-latency non-volatile memory comprises encrypting, by the low-latency non-volatile memory, the durable data in the low-latency non-volatile memory with a non-volatile encryption key, and wherein storing the durable data in the data storage comprises decrypting, by the low-latency non-volatile memory, the durable data.

21. The method of claim 19 , wherein the data storage comprises NAND flash memory and wherein storing the durable data in the data storage comprises storing the durable data in the NAND flash memory.

22. The method of claim 21 , wherein the low-latency non-volatile memory is a byte-addressable write-in-place memory.

23. The method of claim 22 , wherein the byte-addressable write-in-place memory comprises at least one of a chalcogenide phase change material, a 3-dimensional cross point memory, a ferroelectric transistor random-access memory, a nanowire-based non-volatile memory, a phase change memory, a memory that incorporates memristor technology, a magnetoresistive random-access memory (MRAM), and a spin torque transfer MRAM.

24. The method of claim 19 , wherein the data storage comprises byte-addressable, write-in-place non-volatile memory and wherein storing the durable data in the data storage comprises storing the durable data in the byte-addressable, write-in-place non-volatile memory.

25. The method of claim 19 , wherein the data storage comprises a plurality of storage devices in a storage cage and wherein the low-latency non-volatile memory is not in the storage cage.

26. The method of claim 19 , wherein the latency for a storage of the durable data in the data storage is at least ten times the latency for a storage of the durable data in the low-latency non-volatile memory.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2017
From: MILLER, STEVEN C.
To: INTEL CORPORATION
Reel/Frame 041101/0165 →
Continuity (4)
Provisional Application 62427268 · Nov 29, 2016
Provisional Application 62376859 · Aug 18, 2016
Provisional Application 62365969 · Jul 22, 2016
Related Publication 20180024947A1 · Jan 25, 2018
Cited By (4)
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