SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF
A semiconductor device includes a semiconductor substrate, a gate stack and at least one gate spacer. The gate stack is located on the semiconductor substrate. The gate spacer is located on a sidewall of the gate stack. The gate spacer includes a first dielectric feature and a dielectric cap capping the first dielectric feature. The first dielectric feature has a dielectric constant less than that of the dielectric cap.
1 . A semiconductor device, comprising:
a semiconductor substrate;
a gate stack on the semiconductor substrate; and
at least one gate spacer on a sidewall of the gate stack, the gate spacer comprising a first dielectric feature, a second dielectric feature having a bottom above a bottom of the first dielectric feature, a third dielectric feature in contact with the semiconductor substrate and spaced apart from the second dielectric feature, and a dielectric cap capping the first dielectric feature, the first dielectric feature having a dielectric constant less than that of the dielectric cap.
2 . The semiconductor device of claim 1 , further comprising:
an epitaxy structure on the semiconductor substrate, wherein an etch resistance of the dielectric cap to etching a portion of the semiconductor substrate under the epitaxy structure is higher than that of the first dielectric feature.
3 . The semiconductor device of claim 1 , wherein the gate stack is received in a gate trench defined by the at least one gate spacer, and an etch resistance of the dielectric cap to etching the gate trench is higher than that of the first dielectric feature.
4 . The semiconductor device of claim 1 , wherein the dielectric cap is wider than the first dielectric feature.
5 . The semiconductor device of claim 1 , further comprising:
an epitaxy structure on the semiconductor substrate, wherein the second dielectric feature is located between the first dielectric feature and the epitaxy structure, and an etch resistance of the second dielectric feature to etching a portion of the semiconductor substrate under the epitaxy structure is higher than that of the first dielectric feature.
6 . The semiconductor device of claim 1 , wherein the dielectric constant of the first dielectric feature is less than that of the second dielectric feature.
7 . The semiconductor device of claim 1 , wherein the second dielectric feature is located on a sidewall of the first dielectric feature distal to the gate stack.
8 . The semiconductor device of claim 1 , wherein:
the third dielectric feature is between the first dielectric feature and the gate stack, wherein the gate stack is located in a gate trench define by the at least one gate spacer, and an etch resistance of the third dielectric feature to etching the gate trench is higher than that of the first dielectric feature.
9 . The semiconductor device of claim 1 , wherein the dielectric constant of the first dielectric feature is less than that of the second dielectric feature.
10 . The semiconductor device of claim 1 , wherein the third dielectric feature is located on a sidewall of the first dielectric feature proximal to the gate stack.
11 - 12 . (canceled)
13 . The semiconductor device of claim 1 , wherein the second dielectric feature is capped by the dielectric cap.
14 . A semiconductor device, comprising:
a semiconductor substrate;
a gate stack on the semiconductor substrate; and
at least one gate spacer on a sidewall of the gate stack, the gate spacer comprising a first dielectric feature made from a dielectric material and a pair of spaced apart second dielectric features sandwiching the first dielectric feature, the first dielectric feature having a dielectric constant less than those of the second dielectric features.
15 . The semiconductor device of claim 14 , further comprising:
a conductive feature, wherein the first dielectric feature is located between the conductive feature and the gate stack.
16 . The semiconductor device of claim 14 , wherein the gate stack is located in a gate trench defined by the at least one gate spacer, and an etch resistance of the first dielectric feature to etching the gate trench is lower than those of the second dielectric features.
17 . The semiconductor device of claim 14 , further comprising:
an epitaxy structure on the semiconductor substrate, wherein an etch resistance of the first dielectric feature to etching a portion of the semiconductor substrate under the epitaxy structure is lower than those of the second dielectric features.
18 - 20 . (canceled)
21 . A semiconductor device, comprising:
a semiconductor substrate;
a gate stack over the semiconductor substrate; and
a gate spacer extending along a sidewall of the gate stack, the gate spacer comprising first and third dielectric layers spaced apart from the semiconductor substrate and a dielectric cap over the first and third dielectric layers, the dielectric cap and the first and third dielectric layers forming a first interface at a position lower than a top of the gate stack.
22 . The semiconductor device of claim 21 , further comprising:
a second dielectric layer between the first dielectric layer and the gate stack, the second dielectric layer and the dielectric cap forming a second interface continuously extending from the first interface.
23 . The semiconductor device of claim 22 ,
wherein the first dielectric layer is between the second dielectric layer and the third dielectric layer.
24 . The semiconductor device of claim 1 , wherein the dielectric cap and the first and second dielectric features are in contact with the gate stack.
25 . The semiconductor device of claim 21 , wherein the dielectric cap and the first and third dielectric layers are in contact with the gate stack.